Integrated Device Technology, Inc.

Arnaud Biallais

Herve Marie

Fatima Ghanem

Embodiments of a pipeline analog-to-digital converter is provided. In accordance with some embodiments, a pipeline analog-to-digital converter includes a stage, the stage including a residue amplifier that amplifies a residual voltage generated by the stage to obtain an amplified residual voltage; a backend digitizer that digitizes the amplified residual voltage to generate a digitized residual; and a digital correction circuit that corrects the digitized residual according to which zone the digitized residual is found.

Digital extraction and correction of the linearity of a residue amplifier in a pipeline ADC

The present disclosure relates to the field of background estimation in a time-interleaved analog-to-digital converter (ADC). More specifically, the present disclosure relates to systems and methods for background estimation of offset and gain errors in a time-interleaved ADC based on sample count. The error estimation unit of the time-interleaved ADC system includes a counting unit, a subtractor and an integrator. The method for estimating an offset error in a time-interleaved ADC includes determining signs of the signals and outputting corresponding values by the counting unit. The values are further compared and integrated to estimate the offset error. The method for estimating a gain error in a time-interleaved ADC includes determining the absolute values of the signals and comparing the absolute values with a predetermined threshold value. The comparison results are further integrated to estimate the gain error.

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Goneville sur Mer, France

Arnaud Biallais