Broadcom Corporation

Avago Technologies International Sales Pte. Limited

Other

Rockwell International Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Starport Communications, Inc.

Armond Hairapetian

Afshin Momtaz

Jun Cao

Xin Wang

David Chung

Ichiro Fujimori

Guangming Yin

Wee-Guan Tan

Daryush Shamlou

Frederic M Stubbe

Lorenzo Longo

Kang Xiao

Hongtao Jiang

A system is provided that includes a first electronic device, multiple second electronic devices coupled to the first electronic device via respective interfaces, and a clock generator coupled to the second electronic devices and configured to generate and provide a clock signal to each of the second electronic devices for clocking operation of the second electronic devices. The clock signal is a gapped clock signal having at least one gap created by the clock generator removing one or more clock pulses based on a synchronization signal, and the second electronic devices are configured to synchronize data transmission between the second electronic devices and the first electronic device via the interfaces using the at least one gap in the gapped clock signal to align the data transmission.

Synchronization of devices with a gapped reference clock

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (CMOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using CMOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed CMOS logic with low power conventional CMOS logic. The combined CMOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Current-controlled CMOS logic family

Systems, methods and apparatus for transferring data at a high rate. Examples may provide transmitters and receivers that transfer data at a high rate by encoding the data to be transmitted such that the circuits of the transmitter and receiver operate in their high-gain states. The encoded signal may have an average value that is independent of the data that is conveyed by the transmitted signal. In other examples, the encoding may shape the data signal into a data signal having a high-pass characteristic. When the high-pass encoded signal is transmitted through a channel having a low-pass transfer function, the resulting output signal may have much lower ISI compared to a un-encoded input signal. Transmit and receive circuits, such as amplifiers, laser, and photo-diodes, are biased to operate in their high-gain regions when receiving the encoded data in order to provide high-bandwidth and shorter transition times.

Communication systems based on high-gain signaling

A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is transmitted along with single-ended data. By using a periodic signal such a clock signal with approximately 50% duty cycle, a much more stable and accurate reference signal is established for receiving single-ended data.

Universal single-ended parallel bus

The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS)technology using current-controlled CMOS (CMOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using CMOS logic.

Fully differential CMOS phase-locked loop

Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Methods and circuitry for implementing first-in first-out structure

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Glendale, CA, United States of America

Armond Hairapetian