Infineon Technologies Austria Ag

Infineon Technologies Ag

Infineon Technologies Dresden Gmbh & Co . Kg

Infineon Technologies Dresden Gmbh

Other

Armin Willmeroth

Franz Hirler

Anton Mauder

Hans-Joachim Schulze

Uwe Wahl

Hans Weber

Gerald Deboy

Frank Dieter Pfirsch

Markus Schmitt

Carolin Tolksdorf

Winfried Kaindl

Stefan Sedlmaier

Rolf Weis

Michael Rueb

Stefan Gamerith

Markus Zundel

Joachim Weyers

Michael Treu

Holger Kapels

Helmut Strack

Dirk Ahlers

Michael Rüb

Martin Feldtkeller

Matthias Stecher

Bjoern Fischer

Thorsten Meyer

Franz-Josef Niedernostheide

Peter Irsigler

Frank Hille

Christian Fachmann

Holger Ruething

Enrique Vecino Vazquez

Björn Fischer

Marc Fahlenkamp

Carsten Schaeffer

Rudolf Zelsacher

Wolfgang Jantscher

Jens-Peer Stengl

Ahmed Mahmoud

Manfred Pippan

Dietmar Kotz

Hermann Peri

Yann Ruet

Rene Mente

Giulio Fragiacomo

Thomas Wahls

Arunjai Mittal

Roland Rupp

Jenoe Tihanyi

Thoralf Kautzsch

Armin Tilke

Gerhard Noebauer

Erich Griebl

Herbert Schäfer

Roman Knoefler

Holger Huesken

Gabor Mezoesi

Ralf Henninger

Philipp Seng

Jenö Tihanyi

Carsten Schäffer

Thomas Rupp

Andreas Schlögl

Markus Vossebürger

Miguel Cuadron Marion

A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

Power semiconductor device having vertically parallel p-n layers formed in an active region under transistor cells and under a non-depletable extension zone formed in the edge region

A semiconductor device includes a semiconductor body, a vertical transistor arranged in a first device region of the semiconductor body, and a lateral transistor arranged in a second device region of the semiconductor body. The vertical transistor includes a plurality of drift regions of a first doping type and a plurality of compensation regions of a second doping type complementary to the first doping type. The drift regions and the compensation regions are arranged alternately in a lateral direction of the semiconductor body. The second device region includes a well-like structure of the second doping type surrounding a first semiconductor region of the first doping type. The lateral transistor includes device regions arranged in the first semiconductor region.

Half-bridge circuit including integrated level shifter transistor

A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.

Method for producing a transistor device having a superjunction structure

In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.

Method of manufacturing a superjunction semiconductor device

A semiconductor device includes a layer stack with a plurality of first semiconductor layers of a first doping type and a plurality of second semiconductor layers of a second doping type complementary to the first doping type. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers. Each second semiconductor region of the first semiconductor device adjoins at least one of the second semiconductor layers, and is spaced apart from the first semiconductor region. A third semiconductor layer adjoins the layer stack and each first semiconductor region and each second semiconductor region. The third semiconductor layer includes a first region arranged between the first semiconductor region and the second semiconductor region in a first direction. A third semiconductor region of the first or the second doping type extends from a first surface of the third semiconductor layer into the first region.

Semiconductor device and method of producing the same

Method for forming a superjunction transistor device

A power converter circuit includes an inductor and rectifier circuit having an inductor connected in series with an electronic switch, and a rectifier circuit, and a controller for generating a drive signal for driving the electronic switch. The electronic switch has drain, source and gate nodes, drift and compensation cells each including a drift region of a first doping type and a compensation region of a second doping type, and a control structure connected between the drift region of each of the drift and compensation cells and the source node. Each drift region is coupled to the drain node and each compensation region cells is coupled to the source node. A first type doping concentration Nof the drift region is higher than a first doping level L, and a second type doping concentration Nof the compensation region is higher than a second doping level L.

Power converter circuit having a controller for generating a drive signal for driving an electronic switch with high avalanche robustness

A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal, and a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.

Half-bridge circuit including a low-side transistor and a level shifter transistor integrated in a common semiconductor body

A semiconductor device includes an anode doping region of a diode structure arranged in a semiconductor substrate. The anode doping region has a first conductivity type. The semiconductor device further includes a second conductivity type contact doping region having a second conductivity type. The second conductivity type contact doping region is arranged at a surface of the semiconductor substrate and surrounded in the semiconductor substrate by the anode doping region. The anode doping region includes a buried non-depletable portion. At least part of the buried non-depletable portion is located below the second conductivity type contact doping region in the semiconductor substrate.

Semiconductor devices and methods for forming semiconductor devices

A charge-compensation semiconductor device includes a source metallization spaced apart from a gate metallization, and a semiconductor body including opposing first and second sides, a drift region, a plurality of body regions adjacent the first side and each forming a respective first pn-junction with the drift region, and a plurality of compensation regions arranged between the second side and the body regions. Each compensation region forms a respective further pn-junction with the drift region. A plurality of gate electrodes in Ohmic connection with the gate metallization is arranged adjacent the first side and separated from the body regions and the drift region by a dielectric region. A resistive current path is formed between one of the gate electrodes and a first one of the compensation regions, or between the first one of the compensation regions and a further metallization spaced apart from the source metallization and the gate metallization.

Charge-compensation semiconductor device and a manufacturing method therefor

A transistor device includes drain, source and gate nodes, a plurality of drift and compensation cells each including a drift region of a first doping type and a compensation region of a second doping type complementary to the first doping type, and a control structure connected between the drift region of each of the drift and compensation cells and the source node. Each drift region is coupled to the drain node and each compensation region cells is coupled to the source node. A first type doping concentration Nof the drift region is higher than a first doping level L, and a second type doping concentration Nof the compensation region is higher than a second doping level L.

Transistor device with high avalanche robustness

A semiconductor device includes a semiconductor body, which includes transistor cells and a drift zone between a drain layer and the transistor cells. The drift zone includes a compensation structure. Above a depletion voltage a first output charge gradient obtained by increasing a drain-to-source voltage from the depletion voltage to a maximum drain-to-source voltage deviates by less than 5% from a second output charge gradient obtained by decreasing the drain-to-source voltage from the maximum drain-to-source voltage to the depletion voltage. At the depletion voltage the first output charge gradient exhibits a maximum curvature.

VDMOS having a drift zone with a compensation structure

A power semiconductor element having a lightly doped drift and buffer layer is disclosed. One embodiment has, underneath and between deep well regions of a first conductivity type, a lightly doped drift and buffer layer of a second conductivity type. The drift and buffer layer has a minimum vertical extension between a drain contact layer on the adjacent surface of a semiconductor substrate and the bottom of the deepest well region which is at least equal to a minimum lateral distance between the deep well regions. The vertical extension can also be determined such that a total amount of dopant per unit area in the drift and buffer layer is larger than a breakdown charge amount at breakdown voltage.

Power semiconductor having a lightly doped drift and buffer layer

A semiconductor device includes a plurality of compensation regions of a first conductivity type arranged in a semiconductor substrate. The semiconductor device further includes a plurality of drift region portions of a drift region of a vertical electrical element arrangement. The drift region has a second conductivity type. The drift region portions and the compensation regions are arranged alternatingly. At least portions of a border of a depletion region occurring in a static blocking state of the vertical electrical element arrangement are located within the drift region portions at a depth of less than a depth of at least a subset of the compensation regions.

Semiconductor devices and methods for forming a semiconductor device

Disclosed is a transistor device. The transistor device includes: a semiconductor body with an active region and a pad region; at least one transistor cell including a gate electrode dielectrically insulated from a body region by a gate dielectric, wherein the body region is arranged in the active region; an electrode layer arranged above the pad region and dielectrically insulated from the pad region by a further dielectric; and a gate pad arranged above the electrode layer and electrically connected to the electrode layer and the gate electrode of the at least one transistor cell. A thickness of the further dielectric is equal to or less than a thickness of the gate dielectric.

Transistor device with increased gate-drain capacitance

Growing community of inventors

Augsburg, Germany

Armin Willmeroth