Infineon Technologies Ag

Infineon Technologies Dresden Gmbh

Infineon Technologies Dresden Gmbh & Co . Kg

Infineon Technologies Austria Ag

Imec Vzw

Armin Tilke

Danny Pak-Chum Shum

Jiang Yan

Joachim Weyers

Claus Dahl

Hermann Wendt

Dmitri Alex Tschumakow

Chris Stapelmann

Markus Schmitt

Roman Knoefler

Frank Huebinger

Thomas Bertrams

Cajetan Wagner

Bee Kim Hong

Anton Mauder

Stefan Tegen

Ronald Kakoschke

Matthias Hierlemann

Roland Hampp

Martin Seck

Martin Stiftinger

Lincoln O'Riain

Marcus Culmsee

Laura Pescini

Karl Robert Strenz

Franz Hirler

Armin Willmeroth

Hans Weber

Wolfgang Klein

Uwe Wahl

Maik Stegemann

Michael Treu

Christian Fachmann

Michael Beck

Uwe Rudolph

Gabor Mezoesi

Kristin Schupke

Moosung Chae

Manfred Pippan

Jakob Kriz

Katarzyna Kowalik-Seidl

Gopalakrishnan Trichy Rengarajan

Markus Rochel

Thomas Rupp

Patrick Schindler

Thomas Ralf Siemieniec

Andreas Boehm

Gert Jaschke

Markus Wiesinger

Sascha Weber

A semiconductor diode includes a wide bandgap semiconductor body having opposing first and second surfaces. The wide band gap semiconductor body includes a first pn junction diode having a first p-doped region adjoining the first surface and a first n-doped region adjoining both surfaces. The semiconductor diode further includes a semiconductor element including a second pn junction diode having a second p-doped region and second n-doped region, and a dielectric structure between the wide bandgap semiconductor body and semiconductor element. The dielectric structure electrically insulates the wide bandgap semiconductor body from the semiconductor element. The bandgap energy of the semiconductor element is smaller than that of the wide bandgap semiconductor body. A cathode contact is electrically connected to the first n-doped region at the second surface. The second n-doped region of the second pn junction diode is electrically coupled to the first n-doped region of the first pn junction diode.

Semiconductor diode and manufacturing method

A power semiconductor component includes a power semiconductor partial structure having an insulating layer arranged on an upper side of a semiconductor body. A contact hole arranged on an upper side of the insulating layer proceeds from that side, extending at least partly within the insulating layer. An adhesion promoter layer arranged on an upper side of the power semiconductor partial structure at least partly covers the insulating layer upper side and a surface of the contact hole. A tungsten-comprising layer arranged on the adhesion promoter layer at least partly covers the adhesion promoter layer and has a first thickness in a region of the contact hole and dimensioned such that the tungsten-comprising layer fills the contact hole. The tungsten-comprising layer has a second thickness in the region of the insulating layer upper side which is less than the first thickness. A connection layer is arranged on the tungsten-comprising layer.

Contact hole

A semiconductor device includes a semiconductor body having first and second opposing surfaces in a vertical direction, and transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes first and second source regions, first and second body regions, a drift region separated from the respective source region by the corresponding body region, a first gate electrode, and a control electrode. The drift region is arranged between the first and the second body region in a horizontal direction that is perpendicular to the vertical direction and extends from the first surface into the semiconductor body in the vertical direction. The first gate electrode is configured to provide a control signal for switching the transistor cell. The control electrode is configured to provide a control signal for controlling a JFET formed by the first body region, the drift region, and the second body region.

Semiconductor device

In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.

Method of manufacturing a superjunction semiconductor device

A method includes partly removing a supporting layer arranged between a first semiconductor layer and a second semiconductor layer using an etching process to form at least one undercut between the first semiconductor layer and the second semiconductor layer, at least partly filling the at least one undercut with a first material having a higher thermal conductivity than the supporting layer, and forming a sensor device in or on the second semiconductor layer. Semiconductor arrangements and devices produced by the method are also described.

Method for producing a semiconductor arrangement

A method of manufacturing a semiconductor device includes forming an amorphous silicon layer over a first isolation layer. The method further includes simultaneously forming a gate oxide layer of a transistor device and transforming the amorphous silicon layer into a polycrystalline silicon layer by a thermal oxidation process. Herein a cover oxide layer is formed on the polycrystalline silicon layer.

Method of manufacturing a semiconductor device

A bipolar transistor is described. In accordance with one aspect of the present invention the bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has a first crystalline structure and is at least partly doped with dopants of a first doping type. The collector region is laterally enclosed by a trench isolation and is doped with dopants of a second doping type. The transistor further comprises a conductive base contact layer laterally enclosing the base region which is doped with dopants of the first doping type. The base contact layer comprises a part with the first crystalline structure and a part with a second crystalline structure, wherein the part with the second crystalline structure laterally encloses the part with the first crystalline structure. The transistor further comprises an emitter region arranged on the base region, wherein the emitter region is doped with dopants of the second doping type and forming a pn-junction with the base region.

Bipolar transistor

A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a portion of the insulating layer, and the strained silicon layer is disposed on another portion of the insulating layer and has a crystal orientation different from the first crystal orientation.

Silicon-on-insulator chip having multiple crystal orientations

A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor device further includes a transistor structure in the semiconductor body and a source contact structure overlapping the transistor structure. The source contact structure is electrically connected to source regions of the transistor structure. A gate contact structure is further provided, which has a part separated from the source contact structure by a longitudinal gap within a lateral plane. Gate interconnecting structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and a gate electrode of the transistor structure. Electrostatic discharge protection structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and the source contact structure. At least one of the gate interconnecting structures is between two of the electrostatic discharge protection structures along a length direction of the longitudinal gap.

A bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has a first crystalline structure and is at least partly doped with dopants of a first doping type. The collector region is laterally enclosed by a trench isolation and is doped with dopants of a second doping type. The transistor further comprises a conductive base contact layer laterally enclosing the base region which is doped with dopants of the first doping type. The base contact layer comprises a part with the first crystalline structure and a part with a second crystalline structure, wherein the part with the second crystalline structure laterally encloses the part with the first crystalline structure. The transistor further comprises an emitter region arranged on the base region.

A semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further includes a first isolation layer on the first surface of the semiconductor body and a first electrostatic discharge protection structure on the first isolation layer. The first electrostatic discharge protection structure has a first terminal and a second terminal. A second isolation layer is provided on the electrostatic discharge protection structure. A gate contact area on the second isolation layer is electrically coupled to the first terminal of the first electrostatic discharge protection structure. An electric contact structure is arranged in an overlap area between the gate contact area and the semiconductor body. The electric contact structure is electrically coupled to the second terminal of the first electrostatic discharge protection structure and electrically isolated from the gate contact area.

Semiconductor device with electrostatic discharge protection structure

According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon.

Bipolar transistor structure and a method of manufacturing a bipolar transistor structure

Methods of fabricating isolation regions of semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece and at least one trench formed in the workpiece. The at least one trench includes sidewalls, a bottom surface, a lower portion, and an upper portion. A first liner is disposed over the sidewalls and the bottom surface of the at least one trench. A second liner is disposed over the first liner in the lower portion of the at least one trench. A first insulating material is disposed over the second liner in the lower portion of the at least one trench. A second insulating material is disposed over the first insulating material in the upper portion of the at least one trench. The first liner, the second liner, the first insulating material, and the second insulating material comprise an isolation region of the semiconductor device.

Methods of fabricating isolation regions of semiconductor devices and structures thereof

A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and through the insulating material, such that insulating material remains along sidewalls of the first trench. The second trench exposes a portion of the second insulating layer. A semiconductor layer can then be grown within the second trench using the second semiconductor layer as a seed layer.

Mixed orientation semiconductor device and method

Growing community of inventors

Dresden, Germany

Armin Tilke