Siemens Aktiengesellschaft

Infineon Technologies Ag

Qimonda Ag

Other

Infineon Technologies Flash Gmbh & Co. Kg

Qimonda Flash Gmbh

Armin Kohlhase

Hanno Melzner

Josef Willer

Christoph Ludwig

Franz Hofmann

Rex Kho

Thomas B&ouml;hm

Christoph Bilger

Ulrich Zimmermann

Martin Maier

Andreas Rusch

Manfred Hain

Stephan Auer

Yoichi Otani

Achim Schramm

Yann Zinzius

Dominique Savignac

Volker Weinrich

Till Schl&ouml;sser

Herbert Palm

Michael Bollu

Manfred Menke

Alexander Trueby

Alexander Tr&uuml;by

Gerald Higelin

Georg Birkmaier

Friedrich Wienerroither

A system and method is disclosed, including establishing of data connections between electronic devices. One embodiment provides a method for establishing a data connection between a first and a second electronic device, wherein establishing the data connection is authorized by executing at least one action with at least one physical tool.

System and method for establishing data connections between electronic devices

A memory device comprises a memory array and a processing device. The memory array is configured to store a graphic data set. The processing device is configured to initiate outputting of data of the graphic data set from the memory array and to combine the outputted data in response to a read request for providing a graphic content.

Memory for providing a graphic content

Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen the etch hole and form an undercut beneath the gate electrode and at a distance from the ONO storage layer forming the gate dielectric. The undercut is filled, whereby a buried oxide layer of at least 20 nm maximum thickness is formed underneath the channel region. The latter is p-doped at a density of at least 10cm.

Non-volatile memory cell and fabrication method

In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

Semiconductor memory having charge trapping memory cells and fabrication method

Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen the etch hole and form an undercut beneath the gate electrode and at a distance from the ONO storage layer forming the gate dielectric. The undercut is filled, whereby a buried oxide layer of at least 20 nm maximum thickness is formed underneath the channel region. The latter is p-doped at a density of at least 10 cm .

The memory cell configuration has a large number of memory cells provided in a semiconductor substrate and having bit-line trenches which extend in parallel in the longitudinal direction in the main face of the semiconductor substrate, at the bottoms of which in each case a first conductive region is provided, at the peaks of which in each case a second conductive region of the same conduction type as the first conductive region is provided, and in the walls of which in each case an intermediately located channel region is 0 provided; and having word lines which extend in the transverse direction along the main face of the semiconductor substrate, through specific bit-line trenches, to activate transistors provided there. An additional dopant is introduced into the trench walls of the bit-line trenches which are located between the word lines, in order to increase the corresponding transistor turn-on voltage there to suppress leakage currents.

Memory cell configuration and corresponding production process

A read-only memory cell array has vertical MOS transistors formed on trench walls, and is programmed with a programming mask which covers only the areas at which a transistor is not to be produced. As a result, the word lines can be formed with minimum grid spacing and the risk of short-circuiting between adjacent word lines is eliminated by buried ploy stringers.

Read-only memory cell array and method for fabricating it

The memory cell configuration has a multiplicity of preferably ferroelectric memory cells in a semiconductor substrate. Mutually parallel bit line trenches run in the longitudinal direction in the main surface of the semiconductor substrate. Bit lines are disposed in the bottoms of the trenches. Source/drain regions are formed in the crowns of the trenches. Channel regions are provided in the walls of the trenches. The channel region on a wall in each case is configured such that a drivable selection transistor of the relevant memory cell is formed there, while the channel region on the other wall is configured such that the transistor located there is closed. Insulated word lines for driving the selection transistors run in the transverse direction along the main surface of the semiconductor substrate through the bit line trenches. Insulation trenches for insulating the source/drain regions in the longitudinal direction of neighboring memory cells run in the transverse direction in the main surface of the semiconductor substrate. A respective, preferably ferroelectric, capacitor is connected to the source/drain region of the respective memory cell and is arranged above the word lines.

Memory cell configuration and corresponding fabrication method

A memory device includes a multiplicity of memory cells disposed on a substrate for at least intermittent stable storage of at least two different information states. A writing device is associated with the memory cells for selectively putting one of the multiplicity of memory cells into a predetermined information state by external action. A reading device is associated with the memory cells for external detection of a current or chronologically preceding information state of a selected memory cell. The memory cells have a miniaturized mechanical element. The production of such a memory device is performed with the following steps: full-surface application of a first insulator layer onto a main surface of a substrate; full-surface application of a diaphragm layer being formed of an electrically conductive material onto the first insulator layer; structuring of the diaphragm layer in such a way that first conductor tracks are formed, which have enlargements at points of the memory cells; isotropic etching of the first insulator layer, using the structured diaphragm layer as an etching mask, until such time as a sharp point remains behind in the middle, immediately beneath the enlargement; and removal of all of the material of the fist insulator layer on the underside of the enlargement, thus forming a diaphragm.

Method for producing a memory device

Memory device and production method

A semiconductor memory configuration and a manufacturing process for the semiconductor memory configuration use a polishing process in the manufacture of a semiconductor memory configuration with stacked-capacitor-above-bit-line memory cells. At least TC pillars are created with the aid of a CMP step and a completely planarized surface existing prior to the manufacture of the bit line. Further CMP steps are advantageously used, inter alia, in the manufacture of a TB pillar of a bit line which is countersunk in a trench and of a lower capacitor plate, as well as to completely planarize a cell array and a periphery prior to interconnection of the circuit.

Semiconductor memory device having a transistor, a bit line, a word line

Integrated semiconductor circuit or micromechanical component and

A conductor track configuration for very large-scale integrated circuits includes at least two lower conductor tracks extending substantially in a first direction and at least two upper conductor tracks extending substantially in the first direction above the lower conductor tracks. Each of the lower conductor tracks is subdivided into segments, defining gaps between the segments. Each respective one of the segments has one contact leading to the upper conductor track disposed above the one segment. The lower conductor tracks adjacent the segments, as seen in a second direction, have one of the gaps at least in the vicinity of one of the contacts.

Conductor track configuration for very large-scale integrated circuits

Thin layers are deposited on a substrate such as a silicon substrate in series of evacuatable chambers into each of which an inert gas is admitted. In the case of a reactive sputtering deposition, a reactive gas is also admitted. Contamination between neighboring chambers with the reactive gas is prevented, and the chambers are rapidly charged with new reactive gas to achieve a stable gas flow by providing an inlet system including a pair of shut-off valves, and a closable flow governor, the shut-off valves and the flow governor being actuated in synchronism.

Apparatus for applying thin layers onto a substrate

A method for producing consecutive layers of titanium and titanium nitride on a substrate to produce a contact and barrier layer between, for example, aluminum and silicon surfaces or silicide surfaces utilizing cathode sputtering in a one chamber magnetron sputtering system. The titanium and titanium nitride layers each occur as a plurality of individual layers formed in a cyclical process with temperature treatments being carried out between the deposition of the individual layers. During the deposition of the titanium nitride layer, the nitrogen concentration in the reaction gas is adjusted higher than that stoichiometrically required for production of titanium nitride. The resulting combined layers provide low mechanical stressing, good thermal stability, low contact resistance and similar advantages. The method may be employed for the production of megabit-DRAM cells and logic circuits.

Growing community of inventors

Neubiberg, Germany

Armin Kohlhase