Azur Space Solar Power Gmbh

Allos Semiconductors Gmbh

Aixtron Ag

Otto-von-guericke-universität Magdeburg

Otto-von-guericke-universitaet Magdeburg

Osram Opto Semiconductors Gmbh

Albert-ludwigs-universitat Freiburg

Leibniz-institut Fuer Neurobiologie Magdeburg

Azzuro Semiconductors Ag

Laytec Gmbh

Leibniz-institut Für Neurobiologie Magdeburg

Azzurro Semiconductors Ag

Armin Dadgar

Alois Krost

André Strittmatter

Leonhard Michael Reindl

Holger Jurgensen

Holger Jürgensen

Michael Lippert

Frank Ohl

Bertram Schmidt

Martin Deckert

Marc Loschonsky

Fabian Schulze

Thomas Zettler

Christoph Berger

Guenther Strassburger

Florian Hörich

The disclosure relates to a method for growing a semiconductor assembly. The method includes the steps of providing a silicon substrate and growing two metal nitride layers, each metal nitride layer being grown by means of a metal target and a plasma. For the second metal nitride layer a higher hydrogen content is used, allowing for better crystal quality than in known methods. The disclosure further relates to a semiconductor assembly that is produced accordingly.

Method for growing a semiconductor assembly and semiconductor assembly

A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 μmin a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

Nitride semiconductor component and process for its production

A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising:

A semiconductor layer stack, a component made therefrom, a component module, and a production method is provided. The semiconductor layer stack has at least two layers (A, B), which, as individual layers, each have an energy position of the Fermi level in the semiconductor band gap, applying to the layer (A) and applying to the layer (B), with Ethe energy position of the Fermi level, Ethe energy position of the valence band, Ethe energy position of a conduction band and E−Ethe energy difference of the semiconductor band gap E, the thickness of the layers (A, B) being selected in such a way that a continuous space charge zone region over the layers (A, B) results.

Semiconductor layer stack and method for producing same

A semiconductor layer stack, a component made therefrom, a component module, and a production method is provided. The semiconductor layer stack has at least two layers (A, B), which, as individual layers, each have an energy position of the Fermi level in the semiconductor band gap, applying to the layer (A) and applying to the layer (B), with Ethe energy position of the Fermi level, Ethe energy position of the valence band, Ethe energy position of a conduction band and E&#x2212;Ethe energy difference of the semiconductor band gap E, the thickness of the layers (A, B) being selected in such a way that a continuous space charge zone region over the layers (A, B) results.

A micro-electrode array () comprising a flexible substrate () and a multiplicity of electrodes () for electrically measuring neural activity is described. The electrodes () are arranged on the substrate (), project from the plane of the substrate () and have a core (). A plurality of measurement lines () that are electrically insulated from one another are arranged around the core (). Adjacent to the end surface () of the core (), at the end of the electrodes () there are a plurality of electrode surfaces () arranged in a manner distributed spatially around the end surface (), said electrode surfaces in each case being electrically conductively connected to an associated measurement line (). The micro-electrode array () is passivated with a polymer-containing material, such as e.g. polyimide, such that only the electrodes () electrically contact neural tissue with their electrode surfaces (, E, E).

Micro-electrode array and method for producing a micro-electrode array

The invention relates to, inter alia, a light-emitting semiconductor component comprising the following: &#x2014;a first mirror (), &#x2014;a first conductive layer (), &#x2014;a light-emitting layer sequence () on a first conductive layer face facing away from the first mirror, and&#x2014;a second conductive layer () on a light-emitting layer sequence face facing away from the first conductive layer, wherein&#x2014;the first mirror, the first conductive layer, the light-emitting layer sequence, and the second conductive layer are based on a III-nitride compound semiconductor material, &#x2014;the first mirror is electrically conductive, and&#x2014;the first mirror is a periodic sequence of homoepitaxial materials with varying refractive indices.

Light-emitting semiconductor device, light-emitting semiconductor component and method for producing a light-emitting semiconductor device

The invention relates to piezoelectric sensor arrangements, especially sensor arrangements that can be operated in a measuring fluid, in order to be able to detect, for example, elastic properties of the measuring fluid itself or the presence and/or concentration of analyte molecules in the fluid. According to the invention, the sensor arrangement comprises an acoustic resonator which has a sensitive region and is arranged such that a resonance frequency of the sensor arrangement varies according to properties of the measuring fluid. The acoustic resonator is formed by a piezoelectric thin layer resonator and the sensitive region is produced by means of epitaxy, such that transversally polarized vibration modes can be induced.

Piezoelectric sensor arrangement comprising a thin layer shear wave resonator based on epitactically grown piezoelectric layers

Group III nitride layers have a wide range of uses in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and recently Si(111). For the purpose inter alia of integration with Si-CMOS electronics, growth on Si(001) is indicated, which is possible only with difficulty because of the different symmetries and is currently limited solely to misoriented Si(001) substrates, which restricts the range of use. In addition, the layer quality is not at present equal to that produced on Si(111) material. Growth on exactly oriented Si(001) and an improvement in material quality can now be simply achieved by a modification of the surface structure possible with a plurality of methods.

Epitaxial group III nitride layer on (001)-oriented group IV semiconductor

The invention relates to a device and a method for the measurement of the curvature of a surface (), which is more exact and less expensive than prior art devices. The device comprises a light source () for the irradiation of a light beam () onto the surface (), in which a birefingent element () is arranged between light source () and surface (), in which furthermore a detector () is arranged for the detection of the partial beams (), that are reflected from the surface (), and at least one main axis () of the birefringent element () is positioned with respect to the light beam () of the light source () in such a way, that the light beam () of the light source () is split up into at least two parallel beams ().

Device and method for the measurement of the curvature of a surface

This invention relates to a method for depositing III-V semiconductor layers on a non III-V substrate especially a sapphire, silicon or silicon oxide substrate, or another substrate containing silicon. According to said method, a III-V layer, especially a buffer layer, is deposited on the substrate or on a III-V germination layer, in a process chamber of a reactor containing gaseous starting materials. In order to reduce the defect density of the overgrowth, a masking layer consisting of essentially amorphous material is deposited directly on the III-V germination layer or directly on the substrate, said masking layer partially covering of approximately partially covering the germination layer. The masking layer can be a quasi-monolayer and can consist of various materials.

Process for depositing III-V semiconductor layers on a non-III-V substrate

The invention relates to a method for depositing thick III-V semiconductor layers on a non-III-V substrate, particularly a silicon substrate, by introducing gaseous starting materials into the process chamber of a reactor. The aim of the invention is to carry out the crystalline deposition of thick III-V semiconductor layers on a silicon substrate without the occurrence of unfavorable lattice distortions. To this end, the invention provides that a thin intermediate layer is deposited at a reduced growth temperature between two III-V layers.

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Berlin, Germany

Armin Dadgar