Texas Instruments Corporation

Armelle Laine

Laurent A Six

Daniel Mazzocco

Gerald Ollivier

Gilbert Laurenti

Dale E Hocevar

Douglas E Deao

Mark L Buser

Marc Couvrat

Shigeshi Abiko

Jean-Pierre Giacalone

Eric L Badi

Herve Catan

Karim Djafarian

Vincent Gillet

Raphael Defosseux

Francois Theodorou

Yves Masse

Alain Boyadjian

Gael Clave

Jean-Marc Philippe Bachot

Anne Lombardot

Laurent Ichard

Emmanuel Ego

Eric Ponsot

Jack Rosenzweig

Walter A Jackson

Jean-Louis Tardieux

Frederic Nidegger

David Russell

N M Ganesh

A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and path differences and communicate the identified path decisions and the identified path differences to a next ACS stage coupled thereto. The decoder also includes a Traceback unit for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory. The path differences associated with the ACS stage and the next ACS stage provide a reliability estimation of the correctness of the path decisions.

Enhanced viterbi decoder for wireless applications

A digital system is provided with a memory () that can be shared by two or more data requestors (). Two modes of access are provided. In a shared access memory (SAM) access mode, all of the data requestors can sequentially access the memory. In a host only memory (HOM) access mode, a portion () of the memory is connected directly to one of the requestors, such, as a host processor (), so that high bandwidth transfers can be performed. A portion () that is not selected to be in HOM mode can be accessed by other requestors or shut down to save power. The size (S1) of the portion of memory selected for HOM mode is selected to match the requirements of a given application and can be changed by writing a size value to a register.

Shared memory with programmable size

A digital system is provided with a multi-channel DMA controller ( ) for transferring data between various resources ( ). Each channel includes a source port ( ), a channel controller ( ) and a destination port ( ). Channel to port buses (CP -CP ) are representative of parallel buses that are included in the read address bus (RA). Similar parallel buses are provided for a write address bus and a data output bus, not shown. Port to channel buses (PC -PC ) are representative of parallel buses that are included in data input bus DI. Scheduling circuitry ( ) includes request allocator circuitry, interleaver circuitry and multiplexer circuitry and selects one of the channel to port buses to be connected to an associated port controller ( ) on each clock cycle for providing an address for a transaction performed on each clock cycle. The schedulers operate in parallel and source/destination channel addresses are transferred in parallel to each scheduler via the parallel channel to port buses. Input/output data words are also transferred in parallel to/from each port. Each port is tailored to provide an access protocol required by its associated resource. The ports may be tailored to provide an access protocol required by a different type of resource. Channel and scheduling circuitry within a sub-portion ( ) of the DMA controller can interact with various versions of tailored ports without being modified.

Multi-channel DMA with scheduled ports

A digital system is provided with a memory ( ) that can be shared by two or more data requestors ( ). Two modes of access are provided. In a shared access memory (SAM) access mode, all of the data requestors can sequentially access the memory. In a host only memory (HOM) access mode, the memory is connected directly to one of the requestors, such as a host processor ( ), so that high bandwidth transfers can be performed. The HOM access mode is entered when a priority assigned to the host processor is set to be higher than a priority assigned to any other requester. Registers for holding the priority assignments can be written by at least one of the requesters.

Host access to shared memory with a high priority mode

Multi-channel DMA with request scheduling

A processor ( ) is provided that is a programmable fixed point digital signal processor (DSP) with variable instruction length, offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit ( ), a program flow control unit ( ), an address/data flow unit ( ), a data computation unit ( ), and multiple interconnecting busses. Dual multiply-accumulate blocks improve processing performance. A memory interface unit ( ) provides parallel access to data and instruction memories. The instruction buffer is operable to buffer single and compound instructions pending execution thereof. A decode mechanism is configured to decode instructions from the instruction buffer. The use of compound instructions enables effective use of the bandwidth available within the processor. A soft dual memory instruction can be compiled from separate first and second programmed memory instructions. Instructions can be conditionally executed or repeatedly executed. Bit field processing and various addressing modes, such as circular buffer addressing, further support execution of DSP algorithms. The processor includes a multistage execution pipeline with pipeline protection features. Various functional modules can be separately powered down to conserve power. The processor includes emulation and code debugging facilities with support for cache analysis.

Microprocessors

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Armelle Laine