Texas Instruments Corporation

Armando Tresvalles Clarina, Jr

Jovenic Romero Esquejo

Maricel Fabia Escaño

Arvin Cedric Quiambao Mallari

James Raymond Maliclic Baello

Joel Tomas Medina

Floro Lopez Camenforte, Iii

Jay-Ar Tumaru Flores

Ruby Ann Dizon Mamangun

In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer.

Packaged semiconductor device with electroplated pillars

A semiconductor device having a barrier metal layer positioned over a metallization layer, and an under bump metallurgy layer over the barrier metal layer, and a solder bump over the under bump metallurgy layer.

Semiconductor package having a metal barrier

A semiconductor device having a terminal site () including a flat pad () of a first metal covered by a layer () of dielectric material, the layer over the pad parallel to the pad and having a window of a first diameter () exposing the surface of the underlying pad. The terminal site further has a patch-shaped film () of a second metal covering the surface of the exposed first metal and the surface of an annulus of the dielectric layer framing the window, the film patch having a second diameter () greater than the first diameter; and a bump () of a third metal adhering to the film, the bump having a third diameter () smaller than the second diameter, whereby the film protrudes like a flange from the bump.

Semiconductor devices having metal bumps with flange

Growing community of inventors

La Trinidad, Philippines

Armando Tresvalles Clarina, Jr