International Business Machines Corporation

Armand Brunin

Herve L Beranger

Jean-Paul Rousseau

Pierre B Mollier

Gerard Boudon

Bernard A Denis

Guy D'Hervilly

Philippe Stoppa

Bruno Caplier

A DTT type basic logic circuit exhibiting improved immunity to noise and including input diodes for receiving input signals A, B, . . .; an input transistor the emitter of which receives an additional input signal X and the base of which is connected to the anodes of the input diodes; and an output inverter transistor disposed so that the signal at the output thereof represents the logic function X(AB . . .). From this circuit, a family of logic circuits suitable for realizing very-large-scale-integration logic networks in a master slice can be developed. The master slice comprises general-purpose cells in which pre-diffused semiconductor elements can be interconnected to form the desired circuits.

Logic circuits for forming VLSI logic networks

A logic circuit family derived from the conventional 2 level single-ended cascode logic circuit. The basic logic circuit performing a 2--2 OA/AI logic function shown in the attached drawing is given for illustration purposes. It comprises: a logic tree 35 comprised of top and bottom stages 37, 36 dotted at the tree output 38 to perform a determined logic function; the top stage 37 includes a current switch comprised of two input transistors TX34, TX35 connected in a differential amplifier configuration with a reference transistor TX36. The bases of input transistors TX34, TX35 are provided with at least two level shifter devices. Preferably, input level shifter devices are Schottky diodes P31, . . . which move the voltages towards the more positive voltage VPP, to add an AND function on each of these input transistors.

Cascode logic circuit including a positive level shift at the input of

A latch that can serve as a bit storage cell in a random-access store. The latch includes an AND gate (diodes D1 and D2) the input IN of which receives the bit to be stored and the other input of which is connected to a write control line WRL. When no write operation is being performed, transistor T1 is turned off and the state of transistor T2 is dependent on output potential OUT. To perform a write operation, line WRL is activated (goes high) and the state of transistor T3 will depend on the value of the bit applied to input IN. Read operations are performed by means of another AND gate (diodes D4 and D5) and an emitter follower (transistor T4) connected via a bit line BL to an output circuit 2. By adding input transistors and emitter followers to the latch, a multi-port storage can be realized, several rows of which can be simultaneously written into and/or read out.

Latch for storing a data bit and a store incorporating said latch

A method and electronic network for limiting the electrical noise arising during transmission of digital data signals from a first integrated circuit having multiple output devices at which the data signals are formed to the input of a second integrated circuit. The method and network feature steps and means for sensing the conduction state of the first integrated circuit devices and for generating a control signal to invert the data signals before transmission when the number of output devices conducting is equal to or greater than a predetermined number. The method and network also feature steps and means for transmitting the data signals and control signal so that the data signals may be reconstituted to establish the data signals as they appear at the first integrated circuit output, before the data signals are presented to the second integrated circuit input.

Method and network for improving transmission of data signals between

An Exclusive OR circuit with at least two inputs (1 and 2) which exhibits a good immunity to noise. The circuit comprises diodes (D1 and D2) and two transistors (T1 and T2) which have their emitters connected to a reference voltage VR and produce AB at C1. Transistors (T 14 and T5) produce AB at C2, and output transistors (T13 and T6) produce ##STR1## at 3. This circuit can advantageously be used to realize a parity checking circuit.

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Le Mee/Seine, France

Armand Brunin