Intel Corporation

Arlin R Davis

Robert J Woodruff

Jerrie L Coffman

Mark Sean Hefty

William R Magro

David M Lee

Rajesh Sankaran Madukkarumukumana

Harinarayanan Seshadri

Phil C Cayton

Sayantan Sur

Jianxin Xiong

Shiow-wen Wendy Cheng

Roy Larsen

Sean Hefty

Stan C Smith

Shiow-Wen Cheng

William R Margo

Examples described herein relate to configuring a target network interface to recognize packets that are to be written directly from the network interface to multiple memory destinations. A packet can include an identifier that a portion of the packet is to be written to multiple memory devices at specific addresses. The packet is validated to determine if the target network interface is permitted to directly copy the portion of the packet to memory of the target. The target network interface can perform a direct copy to multiple memory locations of a portion of the packet.

Writes to multiple memory destinations

An embodiment includes a low-latency mechanism for performing a checkpoint on a distributed application. More specifically, an embodiment of the invention includes processing a first application on a compute node, which is included in a cluster, to produce first computed data and then storing the first computed data in volatile memory included locally in the compute node; halting the processing of the first application, based on an initiated checkpoint, and storing first state data corresponding to the halted first application in the volatile memory; storing the first state information and the first computed data in non-volatile memory included locally in the compute node; and resuming processing of the halted first application and then continuing the processing the first application to produce second computed data while simultaneously pulling the first state information and the first computed data from the non-volatile memory to an input/output (IO) node.

Low latency cluster computing

Methods, apparatus, and software for optimizing network data flows within constrained systems. The methods enable data to be transferred between PCIe cards in multi-socket server platforms, each platform including a local socket having an InfiniBand (IB) HCA and a remote socket. Data to be transmitted outbound from a platform is transferred from a PCIe card to the platform's IB HCA via a proxied datapath. Data received at a platform may employ a direct PCIe peer-to-peer (P2P) transfer if the destined PCIe card is installed in the local socket or via a proxied datapath if the destined PCIe card is installed in a remote socket. Outbound transfers from a PCIe card in a local socket to the platform's IB HCA may selectively be transferred using an either a proxied data path for larger data transfers or a direct P2P datapath for smaller data transfers. The software is configured to support each of local-local, remote-local, local-remote, and remote-remote data transfers in a manner that is transparent to the software applications generating and receiving the data.

Method to optimize network data flows within a constrained system

A method and device for local area network (LAN) emulation over an Infiniband (IB) fabric. An IB LAN driver at a first node on an IB fabric receives the port and associated local identifier (LID) of one or more remote peer nodes on the IB fabric. An IEEE 802.3 Ethernet MAC address with one LID imbedded is generated. The imbedded LID is for one or more remote peer nodes. The IB LAN driver sends the Ethernet MAC address to an Address Resolution Protocol (ARP). A logical address of a remote peer node is generated by a network protocol. The logical address is mapped to an Ethernet MAC address. The IB LAN driver sends the Ethernet MAC address onto the IB fabric to the one or more remote peer nodes. The remote peer nodes appear to reside on an Ethernet network to the network protocol.

LAN emulation over infiniband fabric apparatus, systems, and methods

Methods, apparatus and systems for facilitating explicit flow control for RDMA transfers using implicit memory registration. To setup an RDMA data transfer, a source RNIC sends a request to allocate a destination buffer at a destination RNIC using implicit memory registration. Under implicit memory registration, the page or pages to be registered are not explicitly identified by the source RNIC, and may correspond to pages that are paged out to virtual memory. As a result, registration of such pages result in page faults, leading to a page fault delay before registration and pinning of the pages is completed. In response to detection of a page fault, the destination RNIC returns an acknowledgment indicating that a page fault delay is occurring. In response to receiving the acknowledgment, the source RNIC temporarily stops sending packets, and does not retransmit packets for which ACKs are not received prior to retransmission timeout expiration.

Explicit flow control for implicit memory registration

Embodiments of the invention describe systems, apparatuses and methods that enable sharing Remote Direct Memory Access (RDMA) device hardware between a host and a peripheral device including a CPU and memory complex (alternatively referred to herein as a processor add-in card). Embodiments of the invention utilize interconnect hardware such as Peripheral Component Interconnect express (PCIe) hardware for peer-to-peer data transfers between processor add-in cards and RDMA devices. A host system may include modules or logic to map memory and registers to and/or from the RDMA device, thereby enabling I/O to be performed directly to and from user-mode applications on the processor add-in card, concurrently with host system I/O operations.

Direct I/O access for system co-processors

Remote direct memory access over a network uses a constrained usage model. In one embodiment, a method of accessing memory on a network comprises a first node of the network generating a remote direct memory access request to remotely access application-level memory on a second node of the network. The first node sends the request in a packet over the network to the second node, the sending being performed in accordance with a constrained usage model. In a further embodiment, constrained usage model comprises sending the packet in an Ethernet protocol packet over an Ethernet network, the Ethernet protocol packet having a OSI layer two header, but not a layer three header.

Network with a constrained usage model supporting remote direct memory access

Each host/node in a network includes a protocol stack (such as TCP/IP), a host channel adapter (HCA) to interface the host to a local network or fabric, and a LAN Emulation (LANE) driver for emulating a LAN network to the protocol stack. Each host in the local network is assigned a global (or legacy) physical address (e.g., a IEEE 802.3 Ethernet MAC address or the like) and a network address (such as an IP address). In addition, the LANE driver maps the global (or legacy) physical address to the local physical address. According to an embodiment, the local physical address is embedded within the global (or legacy) physical address to avoid the use of a specialized ARP protocol. A connection oriented virtual interface (VI) channel is established between a first node and each of the other nodes in the network. The HCA maps the local physical address (e.g., local MAC address) of another node to the VI channel used to communicate with the other node. A standard or legacy ARP message can then be broadcast to the other nodes over the VI channels, and the local physical (e.g., MAC) address of the responding node can be determined from the global or legacy physical address.

Local area network emulation over a channel based network

Provided are a method, system, and article of manufacture. A network communication request is received at an offload application, wherein the offload application interfaces with a first network stack implemented in an operating system and a second network stack implemented in a hardware device. A determination is made if the network communication request can be processed by the second network stack. If the network communication request can be processed by the second network stack, then the network communication request is offloaded for processing to the hardware device.

Method, system, and article of manufacture for network protocols

In an example embodiment, a method of reading data from a remote device transfers data directly from the remote memory of the remote device to the local memory of the local device. A message is sent from the local device to the remote device which includes a transport header indicating the message type of the message. The remote device processes the message to determine whether or not the transport header of the message identifies the message as a type of remote Direct Memory Access (rDMA) read operation. If the message is that type of remote Direct Memory Access (rDMA) read operation, then the remote device performs a remote Direct Memory Access (rDMA) write operation to the local device in accordance with data elements included in the message.

Method of reading a remote memory

A channel based network is provided that allows one or more hosts to communicate with one or more remote fabric attached I/O units. A split-model network driver includes a host module driver and I/O unit module driver. The host module driver and the I/O unit module driver each includes a messaging layer that allows the hosts and I/O units to communicate over the switched fabric using a push-push messaging protocol. For a host to send data, the host either initiates a RDMA write to a pre-registered buffer or initiates a message Send to a pre-posted buffer on the target. For the RDMA case, the initiator would have to send the target some form of transfer indication specifying where the data has been written. This notification can be done with either a separate message or more preferably with immediate data that is included with the RDMA write.

Split model driver using a push-push messaging protocol over a channel based network

An apparatus and method for efficient input/output processing without the use of interrupts is described. The apparatus includes a plurality of descriptors where each descriptor includes a completion indicator and data associated with an input/output request. The plurality of descriptors includes a head descriptor and a tail descriptor. The apparatus further include a plurality of address holders associated with an input/output processor, and each the plurality of address holders is uniquely affiliated with one of the plurality of descriptors. The apparatus further include a polling mechanism for evaluating the completion indicator of the head descriptor and a completion processor for interfacing with the head descriptor. Finally, the apparatus includes connectors between the tail descriptor and address holder and between the input/output processor and the head descriptor.

Growing community of inventors

Yamhill, OR, United States of America

Arlin R Davis