Infineon Technologies Ag

Altis Semiconductor

Arkalgud Sitaram

Christine Dehm

Carlos Mazuré-Espejo

Richard Ferrant

A configuration of resistive memory cells is disclosed. In one embodiment, the configuration of resistive memory cells comprises a plurality of first current lines; a plurality of second current lines; and a plurality of third current lines. A plurality of resistive memory cells being disposed in a memory matrix form between said first and second current lines, said first current lines defining the columns of said memory matrix form, while said second current lines defining the rows of it, wherein each one of the resistive memory cells being connected to one of said first current lines; a plurality of selection transistors having gates and drain-source paths, each drain-source path of said selection transistors being connected to a multiplicity of the resistive memory cells of a row of said memory matrix, said drain-source paths of different selection transistors being connected to a fourth current line (SL), the gates of said selection transistors of a row of said memory matrix form being connected to one of said third current lines. It further relates to a method for sensing the resistance values of a selected resistive memory cell.

Resistive memory cell configuration and method for sensing resistance values

A continuous contact hole is formed in an insulation layer that separates a storage capacitor from a switching transistor. All except a section of the contact hole is filled with poly-Si. A conductive, oxidizable interlayer and a conductive oxygen barrier layer are deposited on the Poly-Si in the remaining section of the contact hole such that the interlayer is completely surrounded by the poly-Si of the contact hole, the insulation layer, and the barrier layer.

Contact-making structure for a ferroelectric storage capacitor and method for fabricating the structure

A storage capacitor, in particular a ferroelectric or paraelectric storage capacitor, and an associated contact-making structure are formed in such a way that the storage capacitor has a first electrode layer, a second electrode layer and a dielectric, ferroelectric or paraelectric capacitor intermediate layer. Proceeding from the plane of the surface of the insulation layer, the storage capacitor extends at least partly into the interior of the via contact and is electrically connected to the via contact.

Storage capacitor and associated contact-making structure and a method for fabricating the storage capacitor and the contact-making structure

A method for fabricating a memory cell, in particular, a DRAM memory cell, having a transistor and a trench capacitor that are connected to one another through a buried strap contact includes applying at least one diffusion barrier on an upper surface of a first filling material of the trench capacitor to prevent an undesirable outdiffusion of dopant from the first filling material. Thus, with the diffusion barrier intact, at most a dopant that is possibly present in a second filling material can outdiffuse into adjoining regions. However, the outdiffusion of dopant from the first filling material can be initiated in a targeted manner by breaking open the diffusion barrier by a thermal treatment. Through the possibility of restraining the diffusion of the dopant until a suitable point in the process, it is possible to avoid an excessive outdiffusion into a contact region with a transistor.

Method for fabricating a memory cell

A method for the fabrication of a gate stack, in particular in very large scale integrated semiconductor memories, uses a combination of a damascene process and a CMP process to produce a gate stack which includes a polysilicon section, a silicide section and a covering-layer section thereabove. The gate stack can be fabricated by using conventional materials, has a very low sheet resistance of <1 ohm/unit area and may carry self-aligning contact sections.

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Fishkill, NY, United States of America

Arkalgud Sitaram