Motorola Corporation

Motorlola, Inc.

Arkalgud R Sitaram

Mark Douglas Hall

Chitra K Subramanian

Olubunmi O Adetutu

James D Hayden

Papu D Maniar

Michael P Woo

Dean J Denning

Robert C Taft

Mousumi Bhat

Craig D Gunderson

James R Pfiester

Jeffrey T Wetzel

Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (,) away from a conductor (,) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (,) is recessed from the edge of the opening (,). When forming a nitride layer (,) within the opening (,), conductive nodules (,) are formed from a portion of the refractory metal containing material (,) such that the conductive nodules (,) lie within the recession (,). In another embodiment, an oxide layer (,) is formed adjacent to the refractory metal containing material (,) before forming a nitride layer (,).

Contact structure and process for formation

Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (52) is recessed from the edge of the opening (32). When forming a nitride layer (54) within the opening (32), conductive nodules (52) are formed from a portion of the refractory metal containing material (20) such that the conductive modules (52) lie within the recession (42). In another embodiment, an oxide layer (82, 102) is formed adjacent to the refractory metal containing material (20) before forming a nitride layer (84, 112).

Method of making a contact structure

A metal-semiconductor layer (26) is formed over an insulating layer (20) such that the metal-semiconductor layer (26) is graded to have varying amounts of the semiconductor and metal throughout the layer. In one embodiment, the metal-semiconductor layer (26) has relatively higher silicon content near the layer's lower and upper surfaces. At the midpoint, the layer is close to stoichiometric tungsten silicide. In another embodiment, a metal-semiconductor-nitrogen layer is formed having nitrogen nearer the lower surface and essentially no nitrogen near the upper surface. The layer (26) can be formed using chemical vapor deposition or sputtering.

Process for forming a semiconductor device

In one embodiment, delamination of a patterned silicon nitride anti-reflective layer (26) from an underlying patterned tungsten silicide layer (32), is prevented by forming a thin silicon layer (30) between the patterned tungsten silicide layer (32) and the overlying patterned silicon nitride anti-reflective layer (26).

Conductive interconnect structure and method of formation

A semiconductor device (10) is formed having an SRAM array with a plurality of SRAM cells. In forming the access and latch transistors, two different gate electrode compositions are used to form the access and latch transistors. More specifically, a dielectric layer (22) is formed between two conductive layers (26 and 28) within the gate electrode (52) for the access transistors while the dielectric layer is not formed between the two conductive layers (26 and 28) for the latch transistors. This structure allows an increase in the beta ratio for the SRAM cell thereby making a more stable SRAM cell without having to use diffused resistors between the access transistors in storage nodes or by having to form a differential thickness between the gate dielectric layers for the latch transistors and the access transistors.

Process for forming a semiconductor device and a static-random-access

Self-aligned silicide regions (24) are formed in a semiconductor device (10) using vapor phase reaction. A chemical vapor deposition system (40) is used, but rather than depositing a blanket silicide material, a precursor (48) is introduced into the reaction chamber (42) and reacts with only exposed silicon and polysilicon members of the device. The reaction is assisted by heating the substrate to a temperature at which the precursor is volatile. Because the precursor source reacts only with exposed silicon and polysilicon regions, subsequent etch steps are unnecessary. In one form, cobalt silicide regions are formed using a cobalt carbonyl as the precursor source.

Method for forming self-aligned silicide in a semiconductor device using

Method of forming conductive interconnect structure

A transition-metal silicide process includes the formation of a boron nitride capping layer overlying a transition-metal layer. In one embodiment, a transition-metal layer (30) is deposited onto a silicon surface (22), and onto a polysilicon gate electrode (12). A capping layer (32), which can be either boron nitride or boron oxynitride is deposited onto the transition-metal layer (30), and an annealing process is carried out to form a transition-metal/silicon alloy layer (34, 36, 38) at the silicon surface (22), and on the gate electrode (12). The capping layer (32) overlies the transition-metal layer (30) during the annealing process and prevents the formation of an oxide layer at the silicon surfaces (22, 12). After the annealing process is complete, the capping layer (13) is removed by a selective wet etch process, and a second annealing step is carried out to form a transition-metal silicide layer (40, 42, 44).

Process for fabricating a silicide layer in a semiconductor device

A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.

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Austin, TX, United States of America

Arkalgud R Sitaram