Intel Corporation

Arkady Bramnik

Alexander Gendler

Ron Gabor

Lev Makovsky

Yiannakis Sazeides

Jose Yallouz

Alex Gerber

In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.

System, apparatus and method for dynamically controlling error protection features of a processor

Described is soft error tolerant flip-flop which comprises hardened sequential elements to reduce latch soft error rate. The flip-flop may include a master latch; and a slave latch coupled to the master latch, wherein only one of the master or slave latch of the flip-flop comprises hardened latch circuitry. For example, only the master latch comprises the hardened latch circuitry.

Flip-flop with soft error tolerance

A method includes calculating, by a processor core, a first residue code of a first packed vector stored in a first vector register of a set of vector registers; calculating a second residue code of a second packed vector stored in a second vector register of the set of vector registers; calculating, from an addition of the first residue code and the second residue code, a reference residue code for a SIMD arithmetic operation; performing an element-by-element execution of the SIMD arithmetic operation between data elements of the first packed vector and of the second packed vector, resulting in an output packed vector; calculating an output residue code of the output packed vector; and detecting an error in the SIMD arithmetic operation based on comparison of the reference residue code with the output residue code.

Advanced error detection for integer single instruction, multiple data (SIMD) arithmetic operations

A processor of an aspect includes a plurality of physical storage locations, and a register rename unit. The register rename unit includes a first register rename storage structure that is to store a given physical storage location identifier, which is to identify a physical storage location of the plurality of physical storage locations, and that is to store a corresponding given one or more redundant bits. The register rename unit also includes a second register rename storage structure. The register rename unit also includes a first conductive path coupling the first and second register rename storage structures. The first conductive path is to convey the given one or more redundant bits end-to-end from the first register rename storage structure to the second register rename storage structure. Other processors are also disclosed, as well as methods and systems.

End-to end transmission of redundant bits for physical storage location identifiers between first and second register rename storage structures

A processor includes physical storage locations, and a register rename unit that includes a plurality of register rename storage structures. At a given time, each of a complete group of physical storage location identifiers is to be stored in one, but only one, of the plurality of register rename storage structures, unless there is an error. Each of the complete group of physical storage location identifiers is to identify a different one of the physical storage locations. The register rename unit is to detect an error when a first value, which is to be equal to an operation on the complete group of the physical storage location identifiers with no errors, is inconsistent with a second value. The second value is to represent the operation on all physical storage location identifiers that are to be stored in the plurality of register rename storage structures at the given time.

Detecting errors in register renaming by comparing value representing complete error free set of identifiers and value representing identifiers in register rename unit

A first codeword may be constructed from a cache tag in a cache and an error correction code corresponding to the cache tag. A second codeword may be constructed from a search tag and an error correction code corresponding to the search tag. A hamming distance may be calculated between the first codeword and the second codeword. If the hamming distance is less than or equal to a threshold, a cache hit may be signaled. If the hamming distance is above the threshold, a cache miss may be signaled.

Efficient cache search and error detection

Double-sensing of a data store being read to increase overall memory read access speed. An indicator signal coupled to the data store being read is responsive to a value stored in the data store. A first sense amplifier has a first input coupled to the indicator signal, a second input coupled to receive a first sense enable signal at a first sense time and an output coupled to provide a first indicated data value responsive to the first sense enable signal and the indicator signal. A second sense amplifier has a first input coupled to the indicator signal, a second input coupled to receive a second sense enable signal at a second sense time, and an output coupled to provide a second indicated data value responsive to the second sense enable signal and the indicator signal. In one embodiment, a first input of a comparator is coupled to the output of the first sense amplifier and a second input of the comparator is coupled to the output of the second sense amplifier. An output of the comparator is coupled to a signal which invalidates the first indicated value if the first indicated value sensed at the first sense time is different than the second indicated value sensed at the second sense time.

Growing community of inventors

Kiryat Motzkin, Israel

Arkady Bramnik