Sandisk Technologies Inc.

Arka Ganguly

Ohwon Kwon

Xiang Yang

Qui V Nguyen

Kou Tei

Chia-Kai Chou

Sirisha Bhamidipati

An apparatus includes a control circuit and a plurality of non-volatile memory cells arranged in a plane of a memory die. The plane includes a first word line including a first word line portion coupled to a corresponding first group of the non-volatile memory cells, and a second word line including a second word line portion coupled to a corresponding second group of the non-volatile memory cells, the second word line different from the first word line. The control circuit is configured to apply a first voltage to the first word line portion and apply a second voltage to the second word line portion to concurrently read the first group of the non-volatile memory cells and the second group of the non-volatile memory cells. The first group of the non-volatile memory cells and the second group of the non-volatile memory cells each store less than a page of data.

Pseudo multi-plane read methods and apparatus for non-volatile memory devices

A storage device is disclosed herein. The storage device, comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines; and a reference current generator circuit configured to receive an input voltage from a voltage supply and generate therefrom a plurality of outputs, each output of the plurality of outputs used to generate one or more bias voltages/currents for one or more control signals. The control circuitry is configured to: receive a refresh read operation command; and adapt operation of the reference current generator circuit based on receiving the refresh read operation command. This proposal is also applicable for other test modes, such as SA stress, soft and preprogram, and SA test modes.

Reference current generator control scheme for sense amplifier in NAND design

Apparatuses, systems, methods, and computer program products are disclosed for an on-die capacitor. A memory chip comprises an array of memory cells. A capacitor is electrically coupled to an array of memory cells. A capacitor receives at least a portion of discharged electricity from an operation for an array of memory cells. A capacitor supplies electricity back to an array of memory cells during a subsequent operation for an array of memory cells.

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Scotts Valley, CA, United States of America

Arka Ganguly