Jariet Technologies, Inc.

Broadcom Corporation

Semtech Corporation

University of Michigan

Ark-Chew Wong

Richard Dennis Alexander

Derek Tam

Joseph Aziz

Andrew Chen

Craig A Hornbuckle

Olivier Nys

Marcel Lugthart

Clifford N Duong

Agnes Woo

Jonathan Muller

Kevin Tunghai Chan

Clark T-c Nguyen

Clark T -c Nguyen

Masashi Yamagata

Olivier Jacques Nys

A band-pass clock distribution circuit includes a clock tree circuit including at least one clock buffer circuit. The clock tree circuit may be configured to receive a first clock signal from a clock generator circuit and to generate a second clock signal based on the first clock signal. A band-pass filter may be configured to receive the second clock signal and to provide a third clock signal to one or more load circuits. The band-pass filter includes a filtering resonant network including a first inductor and a second inductor coupled to one another at a center tap. The filtering resonant network is configurable to resonate with a parasitic capacitance associated with the one or more load circuits. A portion of the band-pass filter is integrated with the clock tree circuit.

Clock distribution circuit with clock tree circuit and filter

A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.

Circuit apparatus for converting digital signals to analog signals including different mode driver circuits

Band-pass clock distribution networks

Digital-to-analog conversion system with current-mode converter and voltage-mode converter

A DAC driver includes a number of DAC drivers coupled to a load network. A first DAC driver includes a first set of data switches that can be controlled by a first digital input signal. The first DAC driver further includes a first set of output switches, a first set of dump switches and a first set of current sources. Another DAC driver includes a second set of output switches, dump switches, and current sources. The first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the first set of current sources to the load network. The first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or the second set current sources into a respective dump load.

Current steering digital-to-analog conversion systems

A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.

Ultra-high speed digital-to-analog (DAC) conversion methods and apparatus having sub-DAC systems for data interleaving and power combiner with no interleaving

A double-balanced radio-frequency (RF) mixing digital-to-analog converter (DAC) apparatus includes a load network, a first set of resistive DAC driver circuits and a first mixing core. The first mixing core can receive first RF input signals from the first set of resistive DAC driver circuits and can provide a first mixed signal to the load network. The first mixing core includes a first input differential pair coupled to two first cross-coupled differential pairs. The first input differential pair can receive first RF input signals at respective first input nodes. Each of the two first cross-coupled differential pairs can receive first positive and negative local oscillator (LO) signals at corresponding first input nodes. The first mixing core can mix the first RF input signals with the first positive and negative LO signals.

RF quadrature mixing digital-to-analog conversion

Hybrid digital-to-analog conversion systems

Examples are provided for converting an analog signal to a digital output signal using serial-ripple analog-to-digital conversion (ADC). An ADC circuit may include conversion stages coupled in series. Each conversion stage may generate a bit for the digital output signal. A data latch may receive bits for the digital output signal from the conversion stages and to provide the digital output signal based on the bits. A conversion stage may include a comparator circuit and a multiplexer circuit. The comparator circuit may compare a sampled input signal with a reference signal and to generate the associated bit of the digital output signal based on a result of the comparison. The multiplexer circuit may provide an associated reference signal to a comparator circuit of a next conversion stage, where the next conversion stage is subsequent to the conversion stage.

Serial-ripple analog-to-digital conversion

A pipeline analog-to-digital converter is disclosed. An example of a pipeline analog-to-digital converter comprises a plurality of stages. Each of the plurality of stages comprises an analog-to-digital conversion circuit comprising a comparator configured to produce an n-bit digital domain output; and a switchable conductance digital-to-analog conversion circuit operatively coupled to the comparator and configured to switch between at least two conductance values in response to a value of the n-bit digital domain output.

Switchable conductance pipeline analog-to-digital conversion

Examples are provided for converting an analog signal to a digital signal by processing more than one bit per cycle in a number of successive approximation cycles. A system may include capacitive sub-DAC circuits and comparators. Switches may isolate the capacitive sub-DAC circuits during one or more first cycles, and merge the sub-DAC circuits during one or more last cycles. A successive approximation register (SAR) may generate digital output signals or DAC digital signals. In another example, a system may include a DAC circuit. An input capacitor may be pre-charged to at least one of an analog input signal and a DAC analog signal. A programmable gain amplifier may amplify an error signal. A multi-bit ADC may convert the amplified error signal to a multi-bit digital signal. An SAR may use the multi-bit digital signal to generate a DAC digital signal or a digital output signal.

Multi-bit successive approximation ADC

Examples of systems and methods are provided for converting an analog input signal to a digital output signal. A system may include a current mode (CM) digital-to-analog converter (DAC) circuit to provide a DAC current. A comparator circuit may be configured to generate a comparator signal in response to an error signal determined based on the DAC current and the analog input signal. A successive approximation register circuit may be configured to generate at least one of a DAC-code signal or the digital output signal, in response to the comparator signal. The DAC-code signal may be used by the CM DAC circuit to control the DAC current.

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Irvine, CA, United States of America

Ark-Chew Wong