Intel Corporation

Arjun Kripanidhi

Kiran Pangal

Balaji Srinivasan

Prashant S Damle

Sanjay Rangan

Hanmant Pramod Belgal

Dany-Sebastien Ly-Gagnon

Lark-Hoon Leem

Sebastian T Uribe

Abhinav Pandey

Hanmant P Belgal

Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed.

Integrated setback read with reduced snapback disturb

Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.

Threshold voltage expansion

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Mountain View, CA, United States of America

Arjun Kripanidhi