Wafertech, Inc.

Arjun Gupta

Ganesh Yerubandi

Pang Leen Ong

Provided is a split-gate embedded flash memory cell and method for forming the same. The flash memory cell includes split-gate transistors in which the control gate is aligned with respect to the floating gate without the use of a photolithographic patterning operation to pattern the material from which the control gates are formed. An anisotropic blanket etching operation is used to form the floating gates of the split-gate floating gate transistors alongside sidewalls of a sacrificial layer. Local oxidation of silicon (LOCOS) methods are not needed to form the inter-gate dielectric and therefore high integrity is maintained for the floating transistor gates. The floating transistor gates are formed of charge storage material such as silicon nitride, SiNin some embodiments.

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Vancouver, WA, United States of America

Arjun Gupta