Sun Microsystems, Inc.

Arjun Dutt

Yi Wu

Dajen Huang

Stephan Hoerold

Yu L Zheng

A method for inserting repeaters in an integrated circuit includes establishing a set of initial constraints for a given set of buses; assigning at least one repeater corresponding to each of the given set of buses based on the set of initial constraints; progressively relaxing the set of initial constraints to form a new set of constraints for a new set of buses and assigning at least one repeater corresponding to each of the new set of buses based on the new set of constraints; and routing assigned repeaters to each of the new set of buses in the integrated circuit.

Converging repeater methodology for channel-limited SOC microprocessors

A mechanism is disclosed for assigning repeaters to signal paths in an integrated circuit design. The mechanism involves reserving, in a first metal layer of the integrated circuit design, metal tracks for routing signals. Access points to a plurality of repeaters are reserved in a second metal layer of the integrated circuit design. Each access point is associated with a particular repeater. The design may have other layers between the second metal layer and a region reserved for the repeaters. The number of repeaters may be based on the number of metal tracks that are available to route signals through the first region. Signal paths are assigned routes that comprise at least a portion of one or more of the metal tracks. A route from signal paths requiring a repeater to access points to a particular repeater is determined. Thus, the signal paths are assigned to a repeater.

Predictable repeater routing in an integrated circuit design

A method for maintaining equivalency between the reference Register Transfer Logic (RTL) and the physical layout design of an integrated circuit by way of maintaining a reference netlist derived from symbolic connectivity.

Fullchip functional equivalency and physical verification

A method for binning and layout of an integrated circuit design which includes providing a table setting forth predefined widths of signal wires and corresponding spacing to shield wires, characterizing effects on timing, noise, and power distribution based on predefined widths and spacing combinations as functions of the length of the signal wire, and laying out the integrated circuit design based upon the predefined widths of signal wires and corresponding spacing to shield wires. The shield wires are adjacent and on both sides of the routed signal wire.

Growing community of inventors

Mountain View, CA, United States of America

Arjun Dutt