Alibaba Group Holding Limited

T-head (shanghai) Semiconductor Co., Ltd.

Arjun Chaudhuri

Chunsheng Liu

Zhibin Xiao

The present invention facilitates efficient and effective information storage device operations. In one embodiment, a system comprises: a plurality of processing cores configured to process information and a debug system coupled to the plurality of cores. The plurality of processing cores are configured to perform respective test operations on the respective processing cores. The debug system is configured to gather results of the test operations on a flexible compaction basis, wherein a compacted indication of a passing test result is available at a debug cluster basis and compacted indications of a failed test result available at the debug cluster basis are further resolved to identify a failing processing core within the cluster. The processing cores are organized in clusters, wherein a set comprising more than one of the plurality of processing cores and less than all of the processing cores is considered a cluster. The processing cores can be organized in levels, wherein the number of processing cores in a cluster differs at different level. The different levels correspond to a debug hierarchy.

Multi-core processor debugging systems and methods

Systems and methods are provided for testing many-core processors consisting of processing element cores. The systems and methods can include grouping the processing elements according to the dataflow of the many-core processor. Each group can include a processing element that only receives inputs from other processing elements in the group. After grouping the processing elements, test information can be provided in parallel to each group. The test information can be configured to ensure a desired degree of test coverage for the processing element that that only receives inputs from other processing elements in the group. Each group can perform testing operations in parallel to generate test results. The test results can be read out of each group. The processing elements can then be regrouped according to the dataflow of the many-core processor and the testing can be repeated to achieve a target test coverage.

Systems and methods for testing many-core processors

A method for testing a many-core processor comprises grouping a plurality of cores in the processor into a plurality of super cores, wherein each super core comprises one or more scan chains that propagate through a respective super core. Further, the method comprises grouping the plurality of super cores into a plurality of clusters. The method also comprises comparing one or more scan chain outputs of respective super cores in each cluster using a network of XOR and OR gates to generate a single bit fault signature for each scan chain in a respective cluster and compacting the single bit fault signatures for each scan chain using a hybrid of spatial and temporal compactors to generate a single bit fault signature for each cluster. The method also comprises method of using a cost function to obtain hierarchical parameters to achieve optimized ATPG effort, area overhead and test time.

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Hangzhou, China

Arjun Chaudhuri