Intel Corporation

Arjan Van De Ven

Asit K Mallick

Vincent J Zimmer

Rajesh Poornachandran

Jason W Brandt

Joseph Nuzman

Robert S Chappell

Peter J Barry

Gopinatth Selvaraje

Lee G Rosenbaum

Julien Carreno

Peter A Dice

Alan Cox

Efraim Rotem

Eliezer Weissmann

Russell Jerome Fenger

Hisham Abu Salah

Deepak Samuel Kirubakaran

Srinivas Pandruvada

Bruce Schlobohm

Arthur Leonard Brown

Fenghua Yu

Jun Pan

Rafal J Wysocki

Julien CARREÑO

Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.

Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacks

In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

Utilization metrics for processing engines

In an embodiment, a system on a chip includes: a single core to execute a legacy instruction set, the single core configured to enter a system management mode (SMM) to provide a trusted execution environment to perform at least one secure operation; and a memory controller coupled to the single core, the memory controller to interface with a system memory, where a portion of the system memory comprises a secure memory for the SMM, and the single core is to authenticate and execute a boot firmware, and pass control to the SMM to obtain a key pair from a protected storage and store the key pair in the secure memory. Other embodiments are described and claimed.

Providing a trusted execution environment using a processor

Various systems and methods for authenticating a user are described herein. A system to includes a biometric scanner to scan an input sequence of biometric identifiers; a storage device to store a biometric identifier database; an input module to receive the input sequence of biometric identifiers; an access module to access the biometric identifier database and retrieve a secret sequence of biometric identifiers; a comparator module to compare the input sequence of biometric identifiers to the secret sequence of biometric identifiers to obtain a result; and an authorization module to, based on the result, allow access to a resource provided by the system.

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Portland, OR, United States of America

Arjan Van De Ven