Qualcomm Incorporated

Ati Technologies Inc.

Ati Technologies Ulc

Ati International Srl

Advanced Silicon Technologies LLC

Aris Balatsos

Milivoje M Aleksic

Kevin O'Neil

Gordon Caruk

Carl K Mizuyabu

Fariborz Pourbigharaz

Charles Leung

Zeeshan S Syed

Andrew Evan Gruber

Greg Sadowski

Grigori Temkine

Oleg Drapkin

Christopher E Koob

George Patsilaras

Song Wang

Serag Gadelrab

Hans Georg Gruber

James Lyall Esliger

Kuldip Sahdra

Wilson Kwan

Sean Sweeney

Simon Booth

Magesh Hariharan

Julio Arceo

Suren Mohan

Siva Raghu Ram Voleti

Peter L Rosefield

Johnny Jone Wai Kuan

Myil Ramkumar

Bhupinder Singh Pabla

Bruce Plotnick

Danny Cheng

Roche Thambimuthu

James L Esliger

Systems and methods relate to managing shared resources in a multithreaded processor comprising two or more processing threads. Danger levels for the two or more threads are determined, wherein the danger level of a thread is based on a potential failure of the thread to meet a deadline due to unavailability of a shared resource. Priority levels associated with the two or more threads are also determined, wherein the priority level is higher for a thread whose failure to meet a deadline is unacceptable and the priority level is lower for a thread whose failure to meet a deadline is acceptable. The two or more threads are scheduled based at least on the determined danger levels for the two or more threads and priority levels associated with the two or more threads.

Bandwidth/resource management for multithreaded processors

A method includes sending data from a first serial low-power inter-chip media bus (SLIMbus) component to a second SLIMbus component. The method further includes sending the data via at least a first SLIMbus data line of a plurality of SLIMbus data lines.

System and method of sending data via a plurality of data lines on a bus

A device includes a processor that is operative to process a data stream such as executable code, encoded video or other suitable data stream, and has a plurality of processor portions. The device further includes a power management controller coupled to the processor portions that controls power consumption of the processor portions based on application profile data associated with the data stream. The application profile data may be included with executable code or provided separately and may directly indicate usage/nonusage of portions of the processor or the data stream may have inherent application profile data in the header that indirectly identifies usage of the processor portions.

Battery-powered device with reduced power consumption based on an application profile data

Techniques of this disclosure provide for adjustment of a conversion rate of a sampling rate converter (SRC) in real-time. The SRC determines relative timing of generated output samples based on non-approximated integer components that are recursively updated. The SRC may further base relative timing of output samples on a value of one or more step size components associated with the integer components. Also according to techniques of this disclosure, a conversion rate of an SRC may be adjusted in real-time based on a detected mismatch between a source clock of a digital input signal and a local clock.

Adjustable sampling rate converter

A portable device includes a controller that is responsive to a remaining power capacity of the battery, and a power consumption level of the portable device and based on user prioritized functional processing capability features, dynamically controls functional processing capability features of the device. The controller provides power for a higher priority feature at the expense of a lower priority functional processing capability feature consistent with the user prioritized functional processing capability features. A wireless portable device is also disclosed that includes a wireless signal strength determinator that determines a received signal strength of the wireless device and a controller that adjusts the functional processing capability feature of the wireless device based on the determined received signal strength and based on battery capacity information. In this way, received signal strength information is used as a further input to determine how to best adjust functional processing capability features of the device.

Portable device with priority based power savings control and method thereof

A technique for adjusting or modifying content delivery to devices is provided, thereby offering a degree of power consumption control in such devices. The device can determine a need to modify power consumption, either in response to an input or via detection of an unfavorable power supply condition. In response, the device sends a request to an infrastructure for at least one reduced rate data stream. Because the at least one reduced rate data stream requires less processing power when undergoing decoding operations, the device subsequently consumes less power. In one embodiment of the present invention, the determination of the unfavorable power supply condition may be based on a configurable power condition profile. Furthermore, subsequent to receiving the at least one reduced rate data stream, the device may provide a request to the infrastructure for at least one increased rate data stream.

Method and apparatus for content delivery to devices

An error detection apparatus and method compares a first hardwired value such as a first clock threshold, and a second hardwired value such as a second clock threshold, and generates an indication that there is an error in a clock signal based on a comparison of the first hardwired value and the second hardwired value to the clock signal. If an error is detected, the error detection apparatus will, for example, interrupt clock recovery logic to take proper action for recovery of a clock generation circuit that generated the clock signal. The clock signal may be generated based on, for example, a reference clock signal that may be provided by an external source clock, or any other suitable source.

Clock error detection apparatus and method

A technique for recording information in a battery operated device is provided such that quality level of the recorded information may be changed 'on the fly.' In one embodiment, while persistently recording information at a first quality level, the battery operated device may, in response to an input a desire or need to change recording quality level, thereafter persistently record the information at a second quality level different from the first quality level, without interrupting the continuity of the recording session. In a presently preferred embodiment, the information being recorded may comprise video information or audio information. Subsequent inputs indicating the need to change recording quality level yet again may also be received thereby causing the battery operated device to persistently record the information at yet another quality level, which quality level may be the same as the first quality level.

Method and apparatus for recording information in battery operated devices

An integrated circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch. The circuit also includes and a power consumption controller in communication with the core-logic, the latch and the isolation circuit, for controlling the latch to store a state of the core-logic output, and output a corresponding signal. The controller is further operable to signal the isolation circuit to isolate the core-logic output from the latch by providing an output corresponding to predetermined value and transition the core-logic from a high power state and a low power state. This prevents transient signals from propagating to interconnected circuit blocks and external devices.

Circuits with transient isolation operable in a low power state

To provide reduced power consumption of a co-processor, a low power dedicated memory is provided. During a low power state, a processing component of the co-processor is instructed to use the low power dedicated memory and a first memory device, normally used by the processing component, is thereafter operated in a reduced power mode for the duration of the low power state. Preferably, the low power dedicated memory has a storage capacity that is significantly less than the storage capacity of the first memory. When an operating state other than the low power state is detected, normal power consumption by the first memory is resumed and the co-processor is directed to use the first memory once again. In this manner, the present invention allows co-processors, and preferably graphics co-processors, to operate in a beneficial low power mode thereby reducing power consumption.

Method and apparatus for reducing power consumption of a co-processor by switching to low power dedicated memory in which image data is periodically updated

A method and apparatus for detecting an error compares a hardwired reference value to a corresponding predetermined value and generates an error indication in response to a change in the predetermined value. In one embodiment, the predetermined value is set to be the same as the hardwired reference value and in response to an electrostatic discharge event or any other suitable cause of error, the predetermined value changes so that a comparison indicates that an error has occurred. An error indication is then generated which may be, for example, an interrupt to recovery logic that generates recovery control information to reset a functional block that was corrupted or to perform in an entire chip reset if desired.

Apparatus and method for detecting and recovering errors caused by electrostatic discharge

A system for generating and applying alpha values is discussed. Different sets of alpha values are generated and stored for each color component of a set of image data associated with a foreground object. A graphics-processing engine processes the foreground object with respect to a background object to be displayed in the same location. Red components of the foreground object are blended with red components of the background object using red-specific alpha values. Blue components of the foreground object are blended with blue components of the background object using blue-specific alpha values and green components of the foreground object are blended with green components of the background object using green-specific alpha values.

System for alpha blending and method thereof

An impedance compensation circuit and method for an input/output buffer provides dynamic impedance compensation by using programmable impedance arrays and a dynamically adjustable on-chip load. Accordingly, among other advantages, only a single off-chip or external calibrated impedance resistor is used and only a single test pad is necessary.

Dynamic impedance compensation circuit and method

A method and apparatus for mapping a linear address to a tiled address that reduces latency between retrieval of pages of data is accomplished when a video graphics processor receives a linear address from the central processing unit and determines whether the linear address is referencing a tiled surface, which is one of up to four portions of the memory. If so, the video graphics processor obtains parameters of the tiled surface. Having obtained the parameters, the video graphics processor determines a normalized linear address based on at least one of the parameters and the linear address. Having done this, the video graphics processor determines a band pointer of the tiled surface based on at least one of the parameters, the normalized linear address and a modular function. In essence, the band pointer points to a normalized initial address of a band of a tiled surface, which includes a plurality of bands. Having obtained the band pointer, the video graphics processor then determines a linear band offset based on the band pointer and at least one of the parameters. Next, a tiled band offset is determined based on the linear band offset. Finally, the tiled address is determined based on the tiled band offset, the band pointer, and at least one of the parameters.

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Toronto, Canada

Aris Balatsos