International Business Machines Corporation

Analog Devices,inc.

Semiconductor Components Industries, LLC

Arindam Raychaudhuri

Diyanesh B Chinnakkonda Vidyapoornachary

Anil Bindu Lingambudi

Sonali Gupta

Colin Gerard Lyden

Edgar Rolando Cordero

Sridhar H Rangarajan

Girisankar Paulraj

William Hunt

Kaushal Kumar Jha

Daniel Lewis

Sumantra Sarkar

Michael D Pardeik

Sushma Nirmala Sambatur

Jhankar Malakar

Sisir Maity

Kaushal Kumar Ja

Michael T Tuthill

David A Phelan

Prem S Swaroop

Imaging circuitry may include half-driver sub-circuits configured to support Mobile Industry Processor Interface (MIPI) D-PHY mode and C-PHY mode. Groups of two half-driver sub-circuits can be coupled together in the D-PHY mode, whereas groups of three half-driver sub-circuits can be coupled together in the C-PHY mode. Each half-driver sub-circuit can include one or more pull-up paths and one or more pull-down paths. Each half-driver sub-circuit can include multiple slices, a first portion of which can be operated to pull in a first direction and a second portion of which can be operated to pull in a second direction opposing the first direction to achieve the desired amount of equalization. The half-driver sub-circuits can be employed as the final driver stage of a shared data path architecture supporting both D-PHY and C-PHY modes. The shared data path can include serializers, pre-driver logic, and/or equalization enable blocks.

MIPI C-PHY and D-PHY interface with shared driver, equalization, and data path circuitry

A system may include multiple electrical components. One electrical component such as an imaging sub-system may be communicatively coupled to another electrical component such as control circuitry for the system. The imaging-subsystem may include transmitter circuitry. The transmitter circuitry can include driver circuitry configured to provide the transmitter circuitry output using a multi-level signaling scheme. To generate the control signals for the driver circuitry, pre-driver combinational logic may precede the serializer circuitry and be coupled to the word data latch circuitry. In such a manner, the generated control signals for different portions of the driver circuitry can be better synchronized with one another, thereby helping improve data EYE margin in the multi-level signal scheme.

Communications channel with multi-level signal transmission

Managing system memory allocation according to a thermal profile defining memory segment policies according to power, performance, and thermal requirements, selecting a defined memory segment policy, implementing a system workload according to the memory segment policy and deploying the system workload according to the implemented memory segment policy.

Thermally aware memory management

Embodiments of the present invention include detecting one or more memory modules coupled to a memory controller via a memory channel. A total power requirement for the one or more memory modules is determined. A voltage regulator module set point of the memory channel is adjusted based at least in part on the power requirement for the one or more memory modules. The voltage regulator module provides power to the memory modules and is characterized by an optimal load current value where the voltage regulator module operates at a peak efficiency. An operating mode of the memory controller is determined. Based on determining that the memory controller is operating in a first mode, the commands serviced by the one or more memory modules are throttled by the memory controller to keep a load current of the memory channel within a range of the optimal load current value.

Memory subsystem power management

A method and a system for monitoring conditions of offline storage devices is disclosed. Predetermined environmental conditions are monitored to determine whether a storage device should be brought online to perform a data integrity check process. The process receives a triggering event that corresponds with the storage device, powers on the storage devices, selects a page from the storage device, and determines a bit error rate. Once the bit error rate is determined, error-correcting code runs to correct the errors. Any uncorrectable errors are reported, and the storage device is brought back offline.

Data retention in storage drives

Methods that can manage power for memory subsystems are provided. One method includes providing power to a set of memory devices via a set of power modules, determining a first amount of power being consumed by the set of memory devices, and in response to a predetermined event, modifying a second amount of power provided to the set of memory devices via a set of spare power modules. Systems and apparatuses that can include, perform, and/or implement the method are also provided.

Power management for memory subsystems

A method, system and memory controller are provided for implementing refresh power optimization during long idle mode in a memory subsystem utilizing Dynamic Random Access Memory (DRAM). The DRAM includes DRAM cells requiring periodic refresh. A DRAM activity monitoring mechanism monitors an instruction queue and asserts a predefined mode register bit when the instruction queue is empty. Responsive to the asserted predefined mode register bit, a refresh rate is increased and a low power mode is established by reducing DRAM core power level for optimizing refresh power during the long idle mode to provide enhanced system performance.

Implementing DRAM refresh power optimization during long idle mode

An apparatus includes a voltage regulation module configured to provide an output voltage signal (Vout) and an auto-calibration module configured to provide a calibration current signal (Isink) corresponding to a voltage difference between a target voltage signal (Vtarget) and the output voltage signal (Vout). The voltage regulation module may adjust the output voltage in response to changes in the calibration current signal. In one embodiment, the voltage regulation module comprises an output voltage resistor pair of resistance Rand R, respectively, and the output voltage signal conforms to the equation Vout=Isink&#xb7;R+Vref&#xb7;(1+R/R).

PVT stable voltage regulator

An apparatus includes a plurality of mirrored transistor pairs configured to provide a first output current, and a second output current that is substantially equal to the first output current. The apparatus also includes a load isolation transistor configured to pass the first output current along to a resistive load and a first and a second biasing transistor configured to bias the load isolation transistor with a load biasing voltage. A gate and drain of the second biasing transistor may be connected to a gate of the load isolation transistor and a drain of the first biasing transistor. Furthermore, a source of the second biasing transistor may be connected to a gate of the first biasing transistor. The width-to-length ratio of the load isolation transistor, the first biasing transistor, and the second biasing transistor are selected to eliminate PTAT dependencies in the first output current.

Reference current circuit architecture

A DAC architecture is provided which is monotonic in operation despite any mismatches in the components. The architecture is a segmented architecture and hence it is area efficient. This is achieved by effecting a generation of analog voltages by driving current sources to resistors in response to digital input. In a preferred embodiment, the invention provides a resistor string coupled between output and vref-, and set of current sources. The current sources are switched to nodes between resistors to generate voltages at the output.

DAC having switchable current sources and resistor string

A technique to provide a higher resolution DAC architecture for converting an N-bit digital word to a corresponding analog voltage signal without increasing chip area and switching capacitance. In one example embodiment, this is accomplished by using a triple string converter. In the triple string converter, a triple switching tree is coupled to a triple resistor string and to an analog output. Each switching tree includes a plurality of switches and each resistor string includes a plurality of corresponding resistors. A logic decoder coupled to the triple switching tree receives an N-bit digital word and generates a digital signal. The plurality of switches in each switching tree is substantially simultaneously controlled by the digital signal to output a range of corresponding analog voltage signals when the triple resistor string is connected across a voltage supply.

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Bengaluru, India

Arindam Raychaudhuri