Xilinx, Inc.

Altera Corporation

Intel Corporation

New York University

Polytechnic University

Arifur Rahman

Stephen M Trimberger

Sean W Kao

Chee Hak Teh

Tim Tuan

Bernhard Friebe

Karthik Chandrasekar

Bernard J New

Tony K Ngai

Kalle M Levon

James B Anderson

Tsunehiro Sai

Ben Zhao

Hong Wang

Christopher F Lane

Venkatesan Murali

Dana How

Hui Liu

Dinesh D Patil

Jeffrey Erik Schulz

Raghunandan Chaware

Hong-Tsz Pan

Robert L Pelt

Satyaki Das

Steven P Young

Michael J Hart

Kyung Suk Oh

Trevor J Bauer

Brian C Gaide

Kaushik Chanda

Ravi Prakash Gutala

Scott J Weber

Patrick J Crotty

Jon M Long

Aravind Raghavendra Dasu

Christopher H Kingsley

Zhaoyin D Wu

Yuanlin Xie

Anirban Rahut

Curt Wortman

Jun Pin Tan

Henley Liu

Myongseob Kim

Ronald L Cline

Chidamber Kulkarni

Cheang-Whang Chang

Chidamber R Kulkarni

Richard Grenier

Bang-Thu Nguyen

Jeffrey Tyhach

Ramakrishna Kishore Tanikella

Wai-Bor Leung

Jinsong Oliver Huang

Dong P Kim

Namhoon Kim

Bahareh Banijamali

Min-Hsing Chen

Jianming Huang

Christopher Perez

Sathaki Das

Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

Integrated circuit device with embedded programmable logic

A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2&#xd7; clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

Scalable 2.5D interface circuitry

A system for running one or more applications is provided. Each application may require memory services that can be accelerated using configurable memory assistance circuits associated with different levels of a memory hierarchy. Integrated circuit design tools may be used to generate configuration data for programming the configurable memory assistance circuits. During compile time, the design tools may identify memory service patterns in a source code, match the identified memory service patterns to corresponding templates, parameterize the matching templates, and then synthesize the parameterized templates to produce the configuration data. During run time, a memory assistance scheduler may map the memory services required by each application to available memory assistance circuits in the system. The mapped memory assistance circuits are programmed by the configuration data to provide the desired memory service capability.

Circuitry with adaptive memory assistance capabilities

A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.

Programmable integrated circuit with stacked memory die for storing configuration data

A computer system includes a processor circuit, first and second memory systems, and a configurable memory assistance circuit. The processor circuit is used to run at least one application. The application issues a memory access operation. The configurable memory assistance circuit is in communication with the first and second memory systems and the processor circuit. The configurable memory assistance circuit accelerates the memory access operation for the application using data as the data is in transit between the first and second memory systems.

Techniques for accelerating memory access operations

Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

Programmable integrated circuits with in-operation reconfiguration capability

An integrated circuit package may include an integrated circuit die having first and second circuit regions and a surface. The first circuit region of the integrated circuit package has an operating temperature that is different than that of the second circuit region. A cooling structure is formed on the surface of the integrated circuit die. The cooling structure includes a group of micropipe interconnects arranged to form a cooling channel that allows for the flow of coolant. The cooling channel includes first and second sub-channels. The first sub-channel has a first size that allows a higher flow rate of the coolant to cool the first circuit region. The second sub-channel has a second size that allows a lower flow rate of the coolant to cool the second circuit region.

Integrated circuit package with enhanced cooling structure

Methods and apparatus for controlling interface circuitry

Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, V.

Using floating gate field effect transistors for chemical and/or biological sensing

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San Jose, CA, United States of America

Arifur Rahman