Intel Corporation

Arif Mahmud

Fangxing Wei

Chamath Abhayagunawardhana

Kianoush Rahbar

A high-speed serial link receiver includes variable offset comparators with centrally controlled offset cancellation. The receiver includes a comparator stage to receive a high-speed differential input signal. Comparator elements of the comparator stage have first and second current sources to provide current to corresponding differential amplifier half-circuits. An offset cancellation controller provides an offset cancellation signal for setting current provided by one of the current sources to at least partially offset an output offset between the differential amplifier half-circuits. A receiver system may be comprised of a plurality of receiver units for receiving a corresponding plurality of channels over high-speed serial links. A state machine may sequentially determine an offset cancellation code for the comparator elements of the receiver units.

High-speed serial link receiver with centrally controlled offset cancellation and method

A tracking loop of an interpolator based receiver includes clock elements that generate a plurality of clocks to sample a signal from a remote transmitter. The tracking loop includes samplers and voter elements that sample the signal with the clocks and generate samples that comparatively indicate a phase relationship between the signal and the clocks. Based on the comparison of the samples in the samplers and voter elements, the tracking loop either sends phase-shift signals to the clock elements to shift the phase of the clocks to match the phase of the signal, or sends a phase-flip signal to the clock elements to flip the clocks if the phase relationship between the signal and the clocks is about 180&#xb0;. Once a phase match between the clocks and the signal is established, the tracking loop remains phase locked with the signal and provides a recovered signal.

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Chandler, AZ, United States of America

Arif Mahmud