Intel Corporation

Ariel Szapiro

Alexander Gendler

Krishnakanth Venkata Sistla

Doron Rajwan

Ankush Varma

Dean A Mulla

Tal Kuzi

Adwait Purandare

Elkana Korem

Nir Tell

Efraim Rotem

Eliezer Weissmann

Nadav Shulman

Nir Rosenzweig

Vivek Garg

Michael Mishaeli

Tsvika Kurts

Ofer Levy

Larisa Novakovsky

Ernest Knoll

Dror Reif

Nazar Syed Haider

Ofer J Nathan

Nimrod Angel

Ido Melamed

Yiftach Gilad

Ariel Sabba

Eric Dehaemer

Arye Albahari

Nir Misgav

Amit Gabai

Shani Rehana

Daniela Kaufman

Gilad Bomstein

Shlomo Attias

Mark Gutman

Eugene Gorkov

An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (P0nMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.

Apparatus and method to detect power supply security attack and risk mitigation

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Power control arbitration

A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

Instruction and logic for parallel multi-step power management flow

Apparatus and methods are provided for improving yield and frequency performance of integrated circuit processors, such as multiple-core processors. In an example, an apparatus can include a plurality of clock buffers, each clock buffer of the plurality of clock buffers configured to receive a first clock signal and distribute a plurality of second clock signals, a one-time programmable locate critical path mechanism configured provide a plurality of indications to enable or disable a delay of each clock buffer of the plurality of clock buffers, and a power management control circuit configured to over-ride one or more of the plurality of indications in a first non-test mode of operation of the apparatus and to not over-ride the one or more indications in a second non-test mode of operation of the apparatus.

Dynamic voltage-level clock tuning

In one embodiment, a processor includes: a core to execute instructions, the core including a plurality of mailbox storages and a trust table to store a trust indicator for each of the plurality of mailbox storages; a first core perimeter logic coupled to the core and including a first storage to store state information of the core when the core is in a low power state; and a second core perimeter logic coupled to the first core perimeter logic and the core, the second core perimeter logic including a second storage to store the state information of the core when the first core perimeter logic is in a low power state. Other embodiments are described and claimed.

Communicating via a mailbox interface of a processor

In one embodiment, a processor includes a credit circuit to communicate credit information between a first clock domain of the processor and a second clock domain of the processor. The credit circuit may include: a loopback path to communicate the credit information between the first clock domain and the second clock domain; and a bypass path to cause the credit information to traverse only a portion of the loopback path, based at least in part on a state of the second clock domain. Other embodiments are described and claimed.

Providing reduced latency credit information in a processor

Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

Changing the clock frequency of a computing device

Systems, apparatus and methods are described related to adaptive support windows for stereoscopic image correlation.

Adaptive support windows for stereoscopic image correlation

A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The method also includes calculating a hamming distance between a) the cache tag and its corresponding ECC and b) the search tag and its corresponding ECC. The method also includes determining if the cache tag matches the search tag by determining if said hamming distance is two or less.

Apparatus and method for fast tag hit with double error correction and triple error detection

A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The method also includes calculating a hamming distance between a) the cache tag and its corresponding ECC and b) the search tag and its corresponding ECC. The method also includes determining if the cache tag matches the search tag by comparing the hamming distance against a threshold.

Apparatus and method for fast tag hit

Growing community of inventors

Tel Aviv, Israel

Ariel Szapiro