Intel Corporation

Ariel Sabba

Alexander Gendler

Larisa Novakovsky

Jason W Brandt

Joseph Nuzman

Lihu Rappoport

Robert S Chappell

Sergiu D Ghetie

Deepak K Gupta

Jared Warner Stark, Iv

Scott P Bobholz

Wojciech S Powiertowski

Efraim Rotem

Krishnakanth Venkata Sistla

Sreenivas Subramoney

Michael Mishaeli

Deborah T Marr

Tsvika Kurts

Sagar V Dalvi

Ofer Levy

Jayesh Gaur

Rodrigo Branco

Scott J Cape

Niv Tokman

Yair Berger

Gilad Holzstein

Julius Yuli Mandelblat

Alexander Lyakhov

Hisham Shafi

Ernest Knoll

Polychronis Xekalakis

Ofer J Nathan

George Leifman

Ariel Szapiro

Lev Makovsky

Shani Rehana

Sumeet Bandishte

Yogesh Bijlani

Anwar Azaarura Zaa'Rura

Afik Sela

Genadi Kazakevich

Alexandra Shainshein

Alexander Gebdler

Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.

Apparatuses and methods for speculative execution side channel mitigation

An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.

Core-only system management interrupt

Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

Changing the clock frequency of a computing device

In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

Restricting clock signal delivery in a processor

In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed.

Reduced power mode of a cache unit

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Karmiel, Israel

Ariel Sabba