Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Sandisk Il Ltd.

Ariel Navon

Shay Benisty

Alexander Bazarsky

Yehuda Hahn

Eran Sharon

Idan Alrod

Alon Marcu

Alex Bazarsky

Dudy David Avraham

Omer Fainzilber

Ran Zamir

Daniel Joseph Linnen

Karin Inbar

Tz-Yi Liu

Ofir Pele

Tianhong Yan

Gadi Vishne

Stella Achtenberg

Opher Lieber

Rami Rom

Noam Presman

William Bernard Boyle

Idan Goldenberg

Alon Eyal

Ofer Shapira

Nika Yanuka

Joshua Lehmann

David Gur

Nian Niles Yang

Itzhak Pomerantz

Julian Vlaiko

Ishai Ilani

Tomer Tzvi Eliash

Philip David Reusswig

Tomer Eliash

David Rozman

Rahav Yairi

Roi Kirshenbaum

Menahem Lasser

Christopher John Petti

Simon Litsyn

Yoav Weinberg

Xinde Hu

Gopinath Balakrishnan

Yan Dumchin

Yuri Ryabinin

Yair Baram

Danny Berler

Wanfang Tsai

Itshak Afriat

Arthur Shulkin

Aki Bleyer

Alexander Kalmanovich

Yoseph Hassan

Micha Yonin

Alexander Tsang-Nam Chu

Guruswamy Ganesh

Vered Kelner

Chris Petti

Tsiko Shohat Rozenfeld

David Avraham

Roy Peretz

Didi Gur

Yonatan Karlik

Edgar Barber

Different operations have different clock rate bottleneck points. For example, during a read operation, the processors may be the bottleneck whereas other operations will not be bottlenecks. Those other operations can have their clock rates reduced to save power since there is no benefit to a higher clock rate as the bottleneck is elsewhere. Predicting the bottleneck would be beneficial. Statistics correlating the bottleneck points with the workload and clock rates are tracked. When the workload changes, the statistics can be consulted to determine where the bottleneck is located and then slow down the clock rates for the non-bottleneck operations. A clock rate table is maintained in the device controller. The table holds the clock rate of each component. Predicting the workload and hence, the clock rates, reduces power consumption, improves performance, and better quality of service (QOS) compatibility characteristics.

Adaptive tuning of memory device clock rates based on usage workloads

Scanning overlap tables for data that is present in cache, but not yet written to the memory device, is time consuming. Performance requirements are increasing as is the size of the overlap table. With the increased size of the overlap table comes a reduction in speed to obtain results of a scan which leads to challenges meeting performance requirements. By providing a cache occupation bitmap, scans can be reduced. Rather than scanning the entire overlap table, a cache occupation bitmap can be searched. When executing a read command, only if the cache occupation bitmap contains an indication that the overlap table has cache data within a range that encompasses the data correlating to the read command will the overlap table be search. In so doing, the overlap table need not be searched when executing every read command, thus allowing achievement of performance requirements more realistic.

Selective scanning of overlap-table in storage memories

Systems, methods, and data storage devices for secured failover access through data storage device side channels are described. Storage devices may include a storage interface and one or more side channels, such as control bus and debug bus interfaces. The different interfaces may use different interface protocols and physical interface connections configured for different types of commands to the data storage device. When a failure of the storage interface occurs, the data storage device may receive a failover message through one or more side channels to reconfigure the side channel interface to receive, execute, and return a response for host storage commands targeting host data on the storage medium.

Secured failover access through data storage device side channels

A data storage device can generate a recommended read threshold value using a model that was trained under a plurality of conditions. However, such a model may result in an undesirable bit error rate or programming latency. If that should occur, the data storage device can use a different model trained under a condition similar to a current condition of the data storage device. In addition to avoiding an undesirable bit error rate or programming latency, this can result in improved throughput, improved quality of service, and reduced power consumption.

Data storage device and method for using multiple models for predicting a read threshold

A system and method are disclosed for flexible emergency power fail management for multiple persistent memory regions. In one embodiment, a method is provided that is performed in a host in communication with a plurality of data storage devices, each data storage device having a persistent memory region, wherein the host comprises a capacitor shared by the plurality of data storage devices. The method comprises determining an allocation of power from the capacitor to each of the plurality of data storage devices; and dynamically changing the allocation of power from the capacitor to at least one data storage device of the plurality of data storage devices. Other embodiments are disclosed.

System and method for flexible emergency power fail management for multiple persistent memory regions

Logical to physical (L2P) tables are implemented in solid state drives (SSDs) to hold L2P address translations. In a thin provisioning or thin storage system, the L2P table is sized to support the total amount of memory that is available to be allocated on a per client or per host basis. During thin provisioning, the total amount of memory is not typically utilized. As such, the L2P table, which is sized to accommodate full usage of the memory allocated, is not fully utilized resulting in unused portions of the L2P table. The unused portions of the L2P table can be reallocated to use as temporal buffers until needed for write commands. Due to the reallocation, less buffers are needed.

Thin provisioning L2P resource sharing

A data storage device has an inference engine that can infer a read threshold based on a non-linear function of inputs that reflect current memory and data conditions. The read threshold can be used in reading a wordline in the memory. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and also improve latency, throughput, power consumption, and quality of service.

Data storage device and method for inferring a read threshold using a time tag determination

A data storage device includes a memory device and a controller coupled to the memory device. When a read threshold calibration operation occurs, less than all of the pages of a representative wordline is sensed, such that read thresholds of less than all of the pages of the representative wordline is obtained. The obtained read thresholds and one or more physical conditions of the representative wordline are provided to a model to obtain the other read thresholds of the remaining pages of the representative wordline that were not sensed. The model correlates read thresholds of one page to another page of the same representative wordline and accounts for the one or more physical conditions of the representative wordline.

Light-weight BES approximation

Before a read threshold is needed to read a wordline in memory, a data storage device can infer a plurality of read thresholds based on possible conditions of the memory that may exist when the read threshold is eventually needed. When the read threshold is needed, it is selected from the previously-inferred read thresholds based on the current conditions of the memory. This can improve latency and throughput, improve quality of service, reduce power consumption, and reduce errors.

Data storage device and method for predicting future read thresholds

Methods and apparatus are disclosed for implementing data augmentation within a storage controller of a data storage device based on machine learning data read from a non-volatile memory (NVM) array of a memory die. Some particular aspects relate to configuring the storage controller to generate augmented versions of training images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device and stored in the NVM array. Other aspects relate to controlling components of the memory die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of the NVM array to inject noise into the images. Data augmentation based on data read from multiple memory dies is also described, such as image data spread across multiple NVM arrays or multiple memory dies.

Storage controller having data augmentation components for use with non-volatile memory die

Splitting an address translation cache (ATC) into two portions can reduce costs and maintain efficient retrieval of data. One portion can be disposed in a first location while a second portion can be disposed in a second location distinct from the first location. The first location can be in the controller. The second location can be in a host memory buffer (HMB) or in a memory device separate from the controller. To obtain translated addresses, untranslated addresses can be searched in the first portion and the corresponding translated addresses can be retrieved from the second portion. When invalidating untranslated addresses, the untranslated addresses of the first portion can be deleted without a need to delete corresponding translated addresses in the second portion. To improve ATC storage capacity, grouping of untranslated addresses is possible using most significant bytes (MSBs).

Hybrid address translation cache using DRAM

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a circuit-bounded array is used to manage updates to time and temperature tag information and to infer read thresholds.

Storage system and method for circuit-bounded-array-based time and temperature tag management and inference of read thresholds

A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.

Enhanced digital signal processor (DSP) NAND flash

Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may be a Neural Turing Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, an NTM controller sets the size of the NTM matrix based on a storage access granularity of the NVM array. For instance, if the NVM reads and writes data in flash memory unit (FMUs), the NTM controller sets the size of the NTM matrix to correspond to the size of an integer number of FMUs. In some examples, the NVM array includes on-chip NTM circuitry configured to perform at least some NTM read head and write head operations. Threshold-based processing is described that can reduce an amount of NTM data read from the NVM array. In other examples, volatile memory is employed rather than an NVM array.

Systems and methods for use with recurrent neural networks

Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANs). In some examples, a GAN-based reconstruction procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Data storage device configured for use with a generative-adversarial-network (GAN)

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Revava, Israel

Ariel Navon