Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Sandisk Il Ltd.

Ariel Navon

Shay Benisty

Alexander Bazarsky

Yehuda Hahn

Eran Sharon

Idan Alrod

Alon Marcu

Alex Bazarsky

Omer Fainzilber

Ran Zamir

Daniel Joseph Linnen

Karin Inbar

Tz-Yi Liu

Ofir Pele

Tianhong Yan

Gadi Vishne

David Avraham

Stella Achtenberg

Opher Lieber

Noam Presman

Rami Rom

William Bernard Boyle

Idan Goldenberg

Ofer Shapira

Nika Yanuka

Joshua Lehmann

David Gur

Nian Niles Yang

Itzhak Pomerantz

Ishai Ilani

Tomer Tzvi Eliash

Dudy David Avraham

Philip David Reusswig

Tomer Eliash

Rahav Yairi

Alon Eyal

Roi Kirshenbaum

Menahem Lasser

Christopher John Petti

Simon Litsyn

Yoav Weinberg

Xinde Hu

Julian Vlaiko

Gopinath Balakrishnan

David Rozman

Yan Dumchin

Yuri Ryabinin

Yair Baram

Danny Berler

Wanfang Tsai

Itshak Afriat

Arthur Shulkin

Aki Bleyer

Alexander Kalmanovich

Yoseph Hassan

Micha Yonin

Alexander Tsang-Nam Chu

Chris Petti

Guruswamy Ganesh

Didi Gur

Yonatan Karlik

Edgar Barber

Roy Peretz

Vered Kelner

Tsiko Shohat Rozenfeld

Methods and apparatus are disclosed for implementing data augmentation within a storage controller of a data storage device based on machine learning data read from a non-volatile memory (NVM) array of a memory die. Some particular aspects relate to configuring the storage controller to generate augmented versions of training images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device and stored in the NVM array. Other aspects relate to controlling components of the memory die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of the NVM array to inject noise into the images. Data augmentation based on data read from multiple memory dies is also described, such as image data spread across multiple NVM arrays or multiple memory dies.

Storage controller having data augmentation components for use with non-volatile memory die

Splitting an address translation cache (ATC) into two portions can reduce costs and maintain efficient retrieval of data. One portion can be disposed in a first location while a second portion can be disposed in a second location distinct from the first location. The first location can be in the controller. The second location can be in a host memory buffer (HMB) or in a memory device separate from the controller. To obtain translated addresses, untranslated addresses can be searched in the first portion and the corresponding translated addresses can be retrieved from the second portion. When invalidating untranslated addresses, the untranslated addresses of the first portion can be deleted without a need to delete corresponding translated addresses in the second portion. To improve ATC storage capacity, grouping of untranslated addresses is possible using most significant bytes (MSBs).

Hybrid address translation cache using DRAM

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a circuit-bounded array is used to manage updates to time and temperature tag information and to infer read thresholds.

Storage system and method for circuit-bounded-array-based time and temperature tag management and inference of read thresholds

A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.

Enhanced digital signal processor (DSP) NAND flash

Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may be a Neural Turing Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, an NTM controller sets the size of the NTM matrix based on a storage access granularity of the NVM array. For instance, if the NVM reads and writes data in flash memory unit (FMUs), the NTM controller sets the size of the NTM matrix to correspond to the size of an integer number of FMUs. In some examples, the NVM array includes on-chip NTM circuitry configured to perform at least some NTM read head and write head operations. Threshold-based processing is described that can reduce an amount of NTM data read from the NVM array. In other examples, volatile memory is employed rather than an NVM array.

Systems and methods for use with recurrent neural networks

Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANs). In some examples, a GAN-based reconstruction procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Data storage device configured for use with a generative-adversarial-network (GAN)

A data storage device and method for device-initiated hibernation are provided. In one embodiment, the data storage device comprises a non-volatile memory and a controller. The controller is configured to: receive, from a host during a set-up phase of a hibernation process, a plurality of write commands with a current state of a volatile memory in the host; store the plurality of write commands in a queue, wherein the plurality of write commands are not executed during the set-up phase of the hibernation process; receive a trigger from the host to perform an execution phase of the hibernation process; and in response to receiving the trigger, execute the plurality of write commands to store the current state of the host's volatile memory in the non-volatile memory of the data storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Data storage device and method for device-initiated hibernation

Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANs). In some examples, a GAN-based decoding (reconstruction) procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure to permit a reduction in the number of parity bits used while storing the data. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Instead of incorporating a single interface towards the host for transferring data, utilizing a designated write-only storage logging device. The write-only storage logging device can accept sequential streams and automatically overwrite. The controller will read the log material in a secure manner using a different and separate physical connection than the one used for write. The storage device may have LBA ranges that work as write-only as well as other LBA ranges, which are normal (both reads and writes are enabled). Both options will allow for a traditional file system as well as sharing the storage, but will still protect the log areas that would be used for events that should not be read out.

Read-protected storage device with sequential logging

More efficient memory device usage is possible by altering the memory device management. For example, when the full storage capacity of the memory device will not be used, certain portions of the memory device can be shut off and then turned on when the storage capacity is needed. When less capacity is needed, data can be consolidated and certain portions of the memory device can be shut off. Additionally, rather than operating in multilevel cell (MLC) memory, the memory device can start in single level cell (SLC) memory and transition to MLC memory over time. If there is a determination that less memory is needed, the memory device can transition from MLC memory to SLC memory. In so doing, the storage capacity of the memory device is more appropriately utilized.

Adaptive use of multiple channels in a storage device

Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

Memory (NVM) devices for use with recurrent neural networks

Rather than using low power mode since there is no indication of a sleep mode type to the data storage device, the sleep mode type is inferred by the data storage device, or supplied by the host. In so doing, the sleep type communication is improved. After the system returns power to the data storage device, there may be a read workload, depending on the sleep type. The workload is characterized by a low-queue depth (QD) sequential read from a specific area of the storage medium that was written to just prior to shut down. In response to inference or host cue, the data storage device will modify an operation so that data storage device is optimized to the sleep mode type, resulting in improved performance and power consumption.

Optimized power up in storage memory devices

The present disclosure generally relates to improved handling of write commands. The host memory buffer (HMB) or other storage space can be utilized to delay execution of host write commands which will improve write performance in different use cases and will also allow having more concurrent streams than open blocks without impacting write or read performance. Generally, once a write command is received, the write command is revised as a new write command that is logically equivalent to the original write command. The revised write command is moved to the HMB along with the data. In so doing, the write command is coalesced and write command handling is improved.

Write coalescing via HMB to optimize write performance

A data storage device and method for race-based data access in a multiple host memory buffer system are provided. In one embodiment, the data storage device stores data in a plurality of host memory buffers in the host instead of in just the host memory buffer usually associated with the data. To read the data, the data storage device sends read commands to all of the host memory buffers. That way, even if some of the host memory buffers are busy, the data can be returned from another one of the host memory buffers. In future reads in similar workloads, a read command can be sent to the host memory buffer that returned the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Data storage device and method for race-based data access in a multiple host memory buffer system

Instead of a system with no awareness to the specific properties of the described system files, such as atomicity of different types of system files, utilize the special characteristics of the corresponding system files to optimize storage handling. A host marks a certain logical block address (LBA) range as belonging to an atomic file. That entire range will be treated as a single atomic unit. Conversely, an LBA range being used to append to a log file may have very small atomic units, allowing for incremental updates without changing the atomicity of the rest of the media. When a write command is passed, the write command will have a certain length. Depending on the length of the write command, the device can disassemble the write command into smaller write sectors of the smallest possible write portion. The device will then write the small write portions to a storage location, while keeping an atomic principle of each of the small write portions.

SSD optimization awareness to atomicity of different system files

Growing community of inventors

Revava, Israel

Ariel Navon