Standard Microsystems Corporation

Ariel Hendel

Kenneth W Brinkerhoff

John D Virzi

Method and apparatus for buffering data packets in a data communication controller environment. In general, the communication controller is interfaceable with a host processor and includes a control unit for accessing a communication medium. Each data packet to be transmitted or received is assigned a unique packet number. Packet number assignment is carried out by a memory management unit which dynamically allocates to each assigned packet number, one or more pages in data packet buffer memory for the storage of the corresponding data packet. If requested storage space is unavailable at the time of request, the memory management unit will allocate a page or pages to an available packet number as the pages become free. Upon issuing the assigned packet number, the physical addresses of the allocated pages of buffer memory storage space are generated in a manner transparent to both the host processor and the control unit. With these physical addresses, a data packet can be accessed from buffer memory, in a simple manner. Upon completion of each data packet loading operation, the corresponding packet number is stored in a packet number queue maintained for subsequent retrieval in order to generate the physical addresses at which the corresponding data packet has been stored.

Method and apparatus for buffering data within stations of a

Method and apparatus are disclosed for buffering data packets in a data communication controller. The communication controller is interfaced with a host processor and includes a control unit for accessing a communication medium. Each data packet to be transmitted or received is assigned a packet number. Packet number assignment is carried out by a memory management unit within the communication controller which dynamically allocates to each assigned packet number one or more pages in a data packet buffer memory for the storage of the corresponding data packet. Upon issuing the assigned packet number, the physical addresses of the allocated pages of data packet buffer memory storage space are generated in a manner transparent to both the host processor and the control unit. Upon completion of each data packet loading operation, the corresponding packet number is stored in a packet number queue maintained for subsequent retrieval in order to generate the physical addresses at which the corresponding data packet has been stored. Also disclosed is a mechanism for automatically generating transmit interrupts to the host processor upon the completion of any preselected number of data packet transmissions determined by the host processor.

Method and apparatus are provided for data communication control within the communication controllers of stations within a local area network. In general, the method and apparatus involves maintaining within the command and status control interface unit of the communication controller, receive and transmit command queues as well as receive and transmit status queues. Pluralities of receive and transmit data packet storage locations are provided for storing data packets to be received as well as transmitted. Each receive command is uniquely associated with a data packet storage location. Receive and transmit commands are buffered in a pipeline manner in the receive and transmit command queues, respectively, whereas receive and transmit status bits are buffered in a pipeline manner in the receive and transmit status queues, respectively. The processor interfacing with the communication controller buffers transmit and receive commands in their respective queues and allocates corresponding data packet storage locations for these commands. The media access control unit of the communication controller executes each command when it is ready according to network protocol, and generates status bits which are buffered in respective status bit queues. The status bits are selectively processed to generate interrupts to the host processor, which can be serviced in due course. As a result of the present invention, consecutive transmission and reception of data packets can be achieved in a manner independent of the operation of the host processor. Consequently, the minimum back-to-back separation between two communication events of the same type, is eliminated thereby improving node and network data throughout.

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Ronkonkoma, NY, United States of America

Ariel Hendel