Intel Corporation

Ariel Gur

Daniel J Ragland

Guy M Therien

Yoav Ben-Raphael

Efraim Rotem

Eliezer Weissmann

Doron Rajwan

Ankush Varma

Russell Jerome Fenger

Eric J DeHaemer

Mark P Seconi

Hisham Abu Salah

David T Mayo

Nadav Shulman

Ernest Knoll

Esfir Natanzon

Ofer J Nathan

Kahraman D Akdemir

Kirk Pfaender

Pavithra Sampath

Ofer Nathan

In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

System, apparatus and method for configurable control of asymmetric multi-threading (SMT) on a per core basis

Systems, methods, and apparatuses relating to hardware control of processor performance levels are described. In one embodiment, a processor includes a plurality of logical processing elements; and a power management circuit to change a highest non-guaranteed performance level and a highest guaranteed performance level for each of the plurality of logical processing elements, and set a notification in a status register when the highest non-guaranteed performance level is changed to a new highest non-guaranteed performance level.

Apparatuses, methods, and systems for hardware control of processor performance levels

Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.

Techniques in phase-lock loop configuration in a computing device

An integrated circuit of an aspect includes a power control unit having an interface to receive an indication that one or more instructions of a first type are to be performed by a core. The power control unit also has logic to control a maximum clock frequency for the core based on the indication that the instructions of the first type are to be performed by the core.

Processors, methods, and systems to adjust maximum clock frequencies based on instruction type

A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine, using a reference voltage/frequency curve, a voltage corresponding to the BCLK frequency rate, wherein the reference V/F curve is generated based on a reference BCLK frequency rate of the processing device.

Method and apparatus for automatic adaptive voltage control

Growing community of inventors

Atlit, Israel

Ariel Gur