Intel Corporation

Ariel Elad Avital

Yossi Ben Simon

Ernest Knoll

Arkady Vaisman

A clock source outputs a clock signal. A first delay line receives a first clock source signal and produces a first output, the first clock source signal at least partially based on the clock signal. A first clock spine receives the first output and produces a global reference clock signal. A second delay line receives a second clock source signal and produces a second output, the second clock source signal at least partially based on the clock signal. A second clock spine receives the second output and produces a global feedback clock signal. A global phase detector detects a phase difference between the global reference clock signal and the global feedback clock signal to produce a global phase detector output. The second clock source signal is controlled at least partially based on the global phase detector output.

Apparatus and method for global to local clock compensation

Techniques and mechanisms for determining an amount of skew between two clock signals. In an embodiment, detector circuitry receives a first signal and a signal which indicate (respectively) a NAND combination of clock signals, and a NOR combination of the clock signals. The detector circuitry evaluates a first length of time that the first signal indicates a respective first logic state, and a second length of time that the second signal indicates a respective second logic state. The skew is calculated based on a difference between the first length of time and the second length of time. In another embodiment, one of the first signal or the second signal is generated with a combinatorial logic gate, a transistor of which is relatively large, as compared to another transistor which is to operate based on one of the first signal, the second signal, or the clock signals.

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Kiryat Bialik, Israel

Ariel Elad Avital