Samsung Electronics Co., Ltd.

Alvarion Ltd.

Ariel Doubchak

Amit Berman

Yaron Shany

Avner Dor

Evgeny Blaichman

Tal Philosof

Dikla Shapiro

Noam Livne

Yoav Shereshevski

Lior Kissos

Eli Haim

Lital Cohen

Naftali Chayat

Nadav Lavi

Danny Stopler

Idan Dekel

Sarit Buzaglo

David Zelikovsky

Rafael Halfon

Elik Almog Sheffi

A method for soft decoding of generalized Reed-Solomon (RS) error correction codes, includes receiving a codeword through a digital electronic communication channel; verifying that an HD error-and-erasures decoding has failed; finding a Groebner basis that accounts for a fixed set of erasures; constructing a Chase and GMD decoding tree on the set of Chase coordinates and the set of GMD coordinates; traversing the decoding tree using polynomials of the Groebner basis as a basis that represents updated coefficient polynomials on the Chase and GMD decoding tree; updating polynomials on the decoding tree using root and derivate steps that flip an edge, or a root step for an erasure edge; calculating error locations by polynomial evaluation of candidate polynomials from the decoding tree, and calculating error values by using Forney's formula; and correcting the received codeword according to the calculated error locations and calculated error values.

Fast combined chase and GMD decoding of generalized Reed-Solomon codes

Provided are a memory system, a method of reading data and a method of finding read thresholds. The method of finding read thresholds includes: selecting a channel distribution among a plurality of channel distributions that corresponds to a read page of the memory device to be read in response to a read command; generating a Trellis diagram based on a decoding scheme and a type of the read page; determining an optimal path through the Trellis diagram using the selected channel distribution according to a dynamic programming algorithm; and finding the read thresholds from the optimal path.

Setting optimal threshold voltages for reading data from a memory device based on a channel distribution

Systems, devices, and methods for encoding information bits for storage, including obtaining information bits; encoding the information bits using an inner code to obtain a plurality of inner code words; encoding the plurality of inner code words using an outer code to generate an outer code word; and storing the outer code word in a storage device, wherein at least one of the inner code and the outer code includes a generalized concatenated code (GCC), and wherein the outer code word includes a hierarchical-GCC (H-GCC) code word.

Generalized hierarchical concatenated codes with fixed dimension and code length

A method of simplified successive cancellation list (SSCL) error decoding of S-polar codes includes representing an S-polar code as a perfect binary tree; providing a node v a vector αof soft information from a parent node; computing a vector αof soft information for a left child of node v; providing node v with a vector βof hard decisions from the left child and using it with αto create a soft information vector αand passing it to a right child of node v; providing node v with a vector βof hard decisions from its right child and using it with βto create a hard decision vector, βof hard decisions, and passing it to its parent node; updating, when v is a ileaf of the perfect tree, two path metrics, and selecting paths obtained by expanding current paths with a lowest path metric.

Acceleration of S-polar ECC throughput by scheduler

A method of correcting data stored in a memory device includes: applying an iterative decoder to the data; determining a total number of rows in first data the decoder attempted to correct; estimating first visible error rows among the total number that continue to have an error after the attempt; estimating residual error rows among the total number that no longer have an error after the attempt; determining second visible error rows in second data of the decoder that continue to have an error by permuting indices of the residual error rows according to a permutation; and correcting the first data using the first visible error rows.

Encoding and decoding of data using generalized LDPC codes

A machine-learning (ML) error-correcting code (ECC) controller may include a hard-decision (HD) ECC decoder optimized for high-speed data throughput, a soft-decision (SD) ECC decoder optimized for high-correctability data throughput, and a machine-learning equalizer (MLE) configured to variably select one of the HD ECC decoder or the SD ECC decoder for data throughput. An embodiment of the ML ECC controller may provide speed-optimized HD throughput based on a linear ECC. The linear ECC may be a soft Hamming permutation code (SHPC).

Machine-learning error-correcting code controller

A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.

Soft reed-solomon decoder for a non-volatile memory

Systems, devices, and methods for encoding information bits for storage, including encoding information bits and balance bits to obtain a first bit chunk of a first arrangement; permuting the first bit chunk to obtain a second bit chunk of a second arrangement; encoding the second bit chunk to obtain a third bit chunk of the second arrangement; permuting a first portion of the third bit chunk to obtain a fourth bit chunk of the first arrangement, and encoding the fourth bit chunk to obtain a fifth bit chunk of the first arrangement; permuting a second portion of the third bit chunk, and adjusting the balance bits based on the fifth bit chunk and the permutated second portion of the third bit chunk; adjusting the first arrangement based on the adjusted balance bits, and obtaining a codeword based on the adjusted first arrangement; and transmitting the codeword to a storage device.

Low gate-count encoding algorithm and hardware of flexible rate GLDPC ECC

A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding includes receiving a codeword x, wherein the received codeword x has &#x3c4;=t+r errors for some r&#x2265;1; computing a minimal monotone basis {&#x3bb;(x)}&#x2286;F[x] of an affine space V={&#x3bb;(x)&#x3f5;F[x]: &#x3bb;(x)&#xb7;S(x)=&#x3bb;'(x) (mod x), &#x3bb;(0)=1, deg(&#x3bb;(x)&#x2264;t+r}, wherein &#x3bb;(x) is an error locator polynomial and S(x) is a syndrome; computing a matrix A&#x2261;(&#x3bb;&#x3b2;)), wherein W={&#x3b2;, . . . , &#x3b2;} is a set of weak bits in x; constructing a submatrix of r+1 rows from sub matrices of r+1 rows of the subsets of A such that the last column is a linear combination of the other columns; forming a candidate error locating polynomial using coefficients of the minimal monotone basis that result from the constructed submatrix; performing a fast Chien search to verify the candidate error locating polynomial; and flipping channel hard decision at error locations found in the candidate error locating polynomial.

BCH fast soft decoding beyond the (d-1)/2 bound

Hierarchical coding architectures and schemes based on multistage concatenated codes are described. For instance, multiple encoder and decoder hierarchies may be implemented along with use of corresponding stages of concatenated codes. The coding scheme generally includes an inner coding scheme (e.g., a polar coding scheme, such as a hybrid polar code or Bose Chaudhuri and Hocquenghem (BCH) code), an outer coding scheme (e.g., a Reed-Solomon (RS) coding scheme), and one or more middle coding schemes. The inner coding scheme is based on a polarization transformation (e.g., polar codes with cyclic redundancy check (CRC) codes, polar codes with dynamic freezing codes, polarization-adjusted convolutional (PAC) codes, etc.) which allows for embedding parity data from an outer code inside a codeword along with the user data. The outer coding scheme has a similar concatenated structure (e.g., of an inner RS code with an outer RS code).

Hierarchical error correction code decoding using multistage concatenated codes

A mobile electronic device may include a memory device and a memory controller including an error correction code (ECC) encoder to encode data, a constrained channel encoder configured to encode an output of the ECC encoder based on one or more constraints, a reinforcement learning pulse programming (RLPP) component configured to identify a programming algorithm for programming the data to the memory device, an expectation maximization (EM) signal processing component configured to receive a noisy multi-wordline voltage vector from the memory device and classify each bit of the vector with a log likelihood ration (LLR) value, a constrained channel decoder configured to receive a constrained vector from the EM signal processing component and produce an unconstrained vector, and an ECC decoder configured to decode the unconstrained vector. A machine learning interference cancellation component may operate based on or independent of input from the EM signal processing component.

Mobile data storage

A hardware architecture for systematic erasure encoding includes first matrix constructor circuit that receives parity-check matrix H for codeword C, and the erased part of codeword C, and outputs matrix Hof columns of H located on erased coordinates of code C; second matrix constructor circuit that receives matrix H and the erased part of codeword C and outputs matrix Hof columns of H located on non-erased coordinates of code C; a neural network that calculates matrix Jthat is an approximate inverse of matrix H. The matrix Jis used to determine new erasures in the parity matrix H and new erased coordinates. Matrices Hand Hare updated, and the updated His provided as feedback to the first matrix constructor circuit. A calculator circuit restores the erased coordinates of codeword C, from the matrix J, matrix H, and a non-erased part of codeword C.

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Ramat Gan, Israel

Ariel Doubchak