Pmc-sierra, Inc.

Pmc-sierra Us, Inc.

Ariel D E Sibley

Graeme Barclay Boyd

Xun Cheng

The invention provides an electrostatic discharge (ESD) protection device for protecting the internal circuitry of an integrated circuit chip from ESD current. The device includes a natively doped substrate having high resistance. A first well is formed in the substrate including a discharge circuit. A second well is formed in the substrate separated from the first well by the width of a natively doped region. The natively doped region has the same connectivity type and substantially the same doping profile as the substrate. During an ESD event, current leaking through the natively doped region between the discharge circuit and the second well creates a voltage that triggers the discharge circuit when reaching its trigger voltage. The resistance ratio between the natively doped region and the well is about 10 times or greater. The high resistance of the natively doped region can achieve the trigger voltage with a smaller ESD current leaking through, which decreases the size of the ESD protection device and increases its performance and sensitivity. Thus, the invention provides for more robust and cost effective ESD protection devices.

Semiconductor device for electrostatic discharge protection

A semiconductor device is provided for preventing Latch-up in Silicon Controlled Rectifiers (SCRs) when these SCRs become activated. Embodiments of the invention use a natively doped region having high resistance to separate the NPN transistor from the PNP transistor that form the SCR, and/or to isolate the entire SCR from the injector source in order to prevent latch-up. The high resistance of the natively doped region allows to achieve the separation resistance needed in a smaller space, as compared to the space required to achieve the same separation resistance in a well. Accordingly, the invention provides for more robust and cost effective latch-up prevention devices.

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Coquitlam, Canada

Ariel D E Sibley