Intel Corporation

Ariel Cohen

Yoel Krupnik

Ram Livne

Amihood Doron

Yitzhak Elhanan Schifmann

Ahmad B Khairi

Gil Shalev

Roee Eitan

Dror Lazar

Ro'ee Eitan

Adee Ofir Ran

Ajay Balankutty

Itamar Levin

Tomer Fael

Alexander Pogrebinsky

Shiva Kiran

Vladislav Tsirkin

Yosi Sanhedrai

Yoav Romach

Omer Cohen

Ilya Kraimer

Marco Cusmai

Hen Sallem

Tali Warshavsky Grafi

Idan Lotan

An apparatus comprising at least one medium to transport a signal and an analog equalization circuit to perform equalization on the signal, wherein the analog equalization circuit comprises independently tunable parameters including a peak frequency gain and a mid-range frequency response slope.

Analog equalization with peaking and slope control

Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.

Differential source follower with current steering devices

A comparator is described. The comparator includes a differential pair having first and second transistors to respectively receive first and second input signals. The comparator also includes a current sink or source transistor coupled to respective source nodes of the first and second transistors. The current sink or source transistor is coupled to receive a fixed bias to keep the current sink transistor active so that large voltage changes on the source nodes is avoided. The comparator circuit includes a latch circuit coupled to respective drain nodes of the first and second transistors. The latch circuit is to reach a final state to present the comparator's output signal. The comparator includes a first switch circuit coupled between the first transistor's drain node and the latch circuit, and a second switch circuit coupled between the second transistor's drain node and the latch circuit. The first and second switch circuits to allow the first and second transistors' respective drain node voltage and source node voltage to enter and exit the comparator's comparison state at a same voltage.

High-speed, low power, low kickback noise comparator suitable for a multi-comparator successive approximation analog-to-digital converter (ADC)

An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.

Analog to digital convertor (ADC) using a common input stage and multiple parallel comparators

One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

Slicer and decision feedback equalization circuitry

Apparatus of a supply generator using dynamic circuit reference is provided which includes: a charge pump to receive a first power supply and to generate a second power supply; a voltage regulator to operate using the second power supply, the voltage regulator having an input to receive a reference and to generate a third power supply; and a reference generator to operate using the first power supply, the reference generator to provide the reference according to an output of a voltage sensing block.

On-chip supply generator using dynamic circuit reference

A multiple-gate field-effect transistor includes a fluid in a top gate, two lateral gates, and a bottom gate. The multiple-gate field-effect transistor also includes a patterned depletion zone and a virtual depletion zone that has a lesser width than the patterned depletion zone. The virtual depletion zone width creates a virtual semiconductor nanowire that is lesser in width than the patterned depletion zone.

Virtual semiconductor nanowire, and methods of using same

A circuit includes a transistor having a biased gate terminal and an input coupled to a bulk terminal. A voltage applied between the bulk terminal and the source terminal modulates the drain-source current. The transistor operates in a saturation region with a bias voltage applied to the gate terminal. The output current is received by a load resistor or an active load.

Body effect amplifier

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Modiin-Makkabbim-Reut, Israel

Ariel Cohen