Intel Corporation

Ariel Berkovits

Altug Koker

Robert L Farrell

Zeev Offen

Thomas A Piazza

Opher D Kahn

Joydeep Ray

David Wyatt

David I Poisner

Blaise B Fanning

Eric C Samson

Aditya Navale

Jon N Hasselgren

Ittai Anati

Alexander Gendler

Nadav Shulman

Michael Mishaeli

Shlomo Raikin

Jim K Nilsson

William A Stevens, Jr

Zvika Greenfield

Julius Yuli Mandelblat

Leslie E Cline

Hisham Shafi

Eran Shifer

Ying Cui

Joseph W Tsang

Michael J Muchnick

Tomas Akenine-Moller

Shani Rehana

Evgeny Bolotin

Mark A Blake

Sameer Desai

Dannie G Feekes

Carl Munkberg

Vijay R Sar-Dessai

A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Technique to share information among different cache coherency domains

A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores.

Flushing and restoring core memory content to external memory

Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

Hybrid exclusive multi-level memory architecture with memory management

Techniques related to graphics rendering including techniques for color compression and/or decompression using adaptive quantization are described.

Lossy color compression using adaptive quantization

A platform may comprise a core coherency domain, graphics coherency domain and a non-coherent domain. A graphics acceleration unit (GAU) of the graphics coherency domain may generate data units from an application and the data units may comprise display data units. The GAU may annotate the display data units with an annotation value before flushing the display data units to an on-die cache. The GAU may identify modified display data units among the display data units stored in the on-die cache and issue flush commands to cause flushing of the modified display data units from the on-die cache to a main memory. The display engine of the non-coherent domain may use the modified display data units stored in the main memory to render a display on a display device.

Ensuring coherence between graphics and display domains

In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

Power management for an integrated graphics device

A method for reducing an importance level of a line in a memory of a cache. An instruction is provided to the cache, the instruction indicating that the line is a candidate for replacement. The importance level of the line may then be reduced based on the instruction. The method may increase cache hit rate and, hence, microprocessor performance.

Method for reducing an importance level of a cache line

Growing community of inventors

Yuvalim, Israel

Ariel Berkovits