Sony Semiconductor Solutions Corporation

Ariel Ben Shem

Itai Shvartz

Zvika Veig

A time-of-flight imaging device comprises an image sensor comprising a pixel array including a plurality of pixel circuits, respective ones of the plurality of pixel circuits including a first tap output configured to output a first tap signal, and a second tap output configured to output a second tap signal; and a signal processing circuit including a time-of-flight processing circuit configured to perform at least one logical operation on the first tap signal and the second tap signal based on a mode of the signal processing circuit, and a counter configured to output a digital signal based on an output of the time-of-flight processing circuit.

Processing circuit and method for time-of-flight image sensor

A time-of-flight device comprises a pixel array including an array of pixel circuits respectively including a photodiode, a first tap, and a second tap; a first signal line coupled to the first tap; a second signal line coupled to the second tap; and processing circuitry coupled to the first signal line and the second signal line, the processing circuitry including: a first comparator configured to receive a first phase signal, to receive a reference signal having an exponential waveform, and to output a first comparison signal, a second comparator configured to receive a second phase signal, to receive the reference signal, and to output a second comparison signal, and a counter configured to perform a count based on the first comparison signal and the second comparison signal.

Q/I calculation circuit and method for time-of-flight image sensor

An analog-to-digital converter comprises a sigma-delta modulator; and an ADC filter configured to store a plurality of partial sums as respective entries in a plurality of lookup tables, retrieve at least one of the plurality of partial sums based on an output of the sigma-delta modulator, and calculate a filter output by adding retrieved ones of the plurality of partial sums together.

Lookup-table-based sigma-delta ADC filter

A latch-based parallel to serial readout circuitry includes latches connected to each other in series and to data inputs in parallel. The latches read in values from the data inputs in parallel, and then output the values serially. A readout control circuitry of the latch-based parallel to serial readout circuitry may cause the latches to read in the values in parallel by switching an active input connection of the latches to the data inputs and enabling the latches simultaneously. The readout control circuitry may cause the latches to readout the values serially by switching an active input connection of the latches to the output of a next latch and sequentially enabling the latches.

Latch based parallel-to-serial readout circuitry and image sensor utilizing the circuitry

A sigma-delta analog-to-digital converter comprises a sigma-delta modulator; and an ADC filter that receives a segment of L binary samples from the sigma-delta modulator, L being a positive integer. The ADC filter includes a predictor circuit that determines whether a power consumption of a first summing method would be higher than a power consumption of a second summing method, based on a content of the segment, and an accumulator circuit that calculates an output using the first summing method in a case where the power consumption of the first summing method would be lower than the power consumption of the second summing method, and using the second summing method in a case where the power consumption of the first summing method would be higher than the power consumption of the second summing method.

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Hasharon, Israel

Ariel Ben Shem