Applied Materials, Inc.

Applied Materials Israel Limited

Appleid Materials, Inc

Ariel Ben-Porath

Youval Nehmadi

Ofer Bokobza

Vicky Svidenko

Jacob Joseph Orbon, Jr

Ayelet Pnueli

Erez Ravid

Gilad Almogy

Dror Shemesh

Mark Wagner

Yair Eran

Rinat Shimshi

Dubi Shachal

Yaron Cohen

Zamir Abraham

Josephine Phua

Evgeny Levin

Alexey Stepanov

Rinat Shishi

Jacob J Orbon, Jr

Gil Sod-Moriah

Chen Ofek

Douglas Ray Hendricks

Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.

Design-based method for grouping systematic defects in lithography pattern writing system

Grouping systematic defects with feedback from electrical inspection

The invention provides a method that includes the stages of: (i) receiving design information representative of a portion of an object that includes sub micron measurement targets, (ii) processing the received design information to provide a large number of measurement targets; and (iii) associating target measurement parameters to each of large number of measurement targets. The invention provides a system that includes: (i) an interface for receiving design information representative of a portion of a layer of an object that includes sub micron measurement targets; and (ii) a processor, coupled to the interface, for processing the received design information to provide a large number of measurement targets; and for associating target measurement parameters to each of large number of measurement targets.

Process monitoring system and method for processing a large number of sub-micron measurement targets

A method for electrically testing a semiconductor wafer during integrated-circuit fabrication process, the method including: (i) providing a scanning charged-particle microscope (SCPM), having a defined scanning plane and operative, while in any one mechanical state, to scan a surface in the scanning plane within a two-dimensional scanning window, which has a given maximum size; (ii) providing in association with any layer of the wafer, it being a test layer, one or more test structures, each test structure including normally conductive areas within a normally non-conductive background in one or more layers, which include said test layer, the conductive areas formed as one or more patterns; the patterns in said test layer include one or more clusters of mutually isolated pads; each pad is conductively connected with a corresponding distinct point on the patterns and all the pads in any one cluster are sized and arranged so that at least a significant portion of each pad falls within a common window whose size does not exceed said maximum size of said scanning window; (iii) with said test layer forming the top surface of the wafer, placing the wafer on the SCPM and adjusting the mechanical state of the SCPM so that at least a significant portion of each pad in any one of said clusters is within said scanning window; (iv) causing the SCPM, while in said mechanical state, to scan all of the pads of said one cluster and thereby to provide information about the electrical state of the respective test structure.

Voltage contrast test structure

A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.

Design-based monitoring

A method and apparatus is provided for automatically classifying a defect on the surface of a semiconductor wafer into one of, e.g., seven core classes: a missing pattern on the surface, an extra pattern on the surface, a deformed pattern on the surface, a particle on the surface, a particle embedded in the surface, a particle and a deformed pattern on the surface, or craters and microscratches on the surface. The defect may also be further classified into a subclass of arbitrarily defined defects defined by the user or preprogrammed in the apparatus. Embodiments include using a scanning electron microscope (SEM) capable of collecting electrons emitted from a plurality of angular sectors to obtain an image of the defect and a reference image containing topographical and location information, then analyzing this information to classify the defect. As the defects are classified, counts are maintained of the number of occurrences of each type of defect, and an alarm is raised if the defect count in a particular class exceeds a predetermined level. Thus, defects are accurately and reliably classified and monitored to enable early detection and cure of processing problems.

Automatic defect classification with invariant core classes

A method and apparatus is provided for automatically classifying a defect on the surface of a semiconductor wafer into one of a predetermined number of core classes using a core classifier employing boundary and topographical information. The defect is then further classified into a subclass of arbitrarily defined defects defined by the user with a specific adaptive classifier associated with the one core class and trained to classify defects only from a limited number of related core classes. Defects that cannot be classified by the core classifier or the specific adaptive classifiers are classified by a full classifier.

Hybrid invariant adaptive automatic defect classification

A kill index classification method for prioritizing relational aspects of topological defect intersections, particularly in association with an intermediate analytical testing stage of a multi-stage semiconductor fabrication process. The method relates to an analysis of the geometrical relationship between non-predetermined portion(s), generally referred to as defects, and the surrounding predetermined topology of a conductive semiconductor pattern, to determine the effect of defects on the functionality and reliability of a wafer, and particularly an examined die thereon. Further, in accordance with this geometrical information, a preferred classification of the effects of defects into a numerical value, the &ldquo;kill index&rdquo;, is achieved. Preferably, this kill index is strongly linked, correlated and related to the damage caused by the defect to the functionality and/or reliability of the underlying integrated circuit.

Kill index analysis for automatic defect classification in semiconductor wafers

A system and method for directing the object, such as a semiconductor die. The system includes a first images such as a scanning electron microscope, a stage for moving the object and a second imager and miller such as a focused ion beam generator. The object is images to locate a desired location in which the object is to be milled and a landmark that is utilized for directing the miller. The system can include additional steps of milling, analyzing and movement of the object.

System and method for directing a miller

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Gealya, Israel

Ariel Ben-Porath