U.S. Philips Corporation

U.S. Phillips Corporation

Arie Slob

Cornelis Maria Hart

Ties S Te Velde

Jan W Slotboom

Marcellinus J Pelgrom

Hendrikus J Veendrick

Cornelis Am Mulder

Hendrik A Harwig

Geert J Davids

Pierre G Jansen

Cornelis Glm Van Der Sanden

Albert Schmitz

Wiegert Wiertsema

Ferdinand Camerik

Karel E Kuyk

Carel S Scholten

A charge-coupled device has a series register (A) having charge storage electrodes (3a) for defining charge storage wells and charge transfer electrodes (3b) for transporting charge between the charge storage wells and a parallel section (C) having channels (1a,1b) extending transversely of the series register (A). The parallel section (C) has charge storage electrodes (11a,12a,13a . . . Na) spaced apart along the channels, (1a,1b) to define a respective charge storage well with each channel to provide a respective row of charge storage wells extending transversely of the channels and has charge transfer electrodes (12b . . . Nb) for transferring charge between adjacent rows of charge storage wells, and a transfer gate (T1) for transferring charge between the series register (A) and an adjacent row of charge storage wells defined by the channels (1a,1b) and a first charge storage electrode (11a) of the parallel section. The first charge storage electrode (11a) of the parallel section (C) is shaped so that, at least over each channel (1a,1b), the first charge storage electrode (11a) is wider than succeeding charge storage electrodes (12a, . . . Na) of the parallel section (C).

Charge-coupled device having reduced cross-talk

A first charge storage electrode (21) has a first row (21b) of teeth interdigitated with a second row (22b) of teeth of a second charge storage electrode (22). The second storage electrode (22) has a third row (22c) of teeth interdigitated with a fourth row (23b) of teeth of a third charge storage electrode (23). The first and third rows (21b and 22c) overlie one group (11b) of a series of parallel conduction channels while the second and fourth rows (22b and 23b) overlie another group (11a) of the parallel channels. A first charge transfer electrode (24) is provided to transfer charge packets into sites beneath the first storage electrode. Second, third, fourth and fifth charge transfer electrodes (25, 26, 27 and 28) are provided to transfer charge packets between sites beneath, respectively, the first storage electrode (21) and the second row (22b), the first row (21b) and the second storage electrode (22), the second storage electrode (22) and the fourth row (23b), and the third row (22c) and the third storage electrode (23). The first, second and third storage and associated transfer electrodes may form an output stage (20) of a parallel register (C) of a series-parallel-series device to enable de-interlacing of rows of information.

Charge-coupled device

In dynamic memories, generally a fluctuation of 10% of the nominal value of the supply voltage is allowed. Since, when reading, the input gate is applied to the supply, this fluctuation in the supply results in 20% of fluctuation in the charge packet formed below the input gate. In order to eliminate this fluctuation and hence to increase the permitted interference margin for other interference sources, a voltage stabilization circuit is arranged between the supply voltage and the input gate so that the fluctuation in the supply also occurs at the source zone, as a result of which the size of the charge packet becomes independent of the supply. For the voltage stabilization circuit, use may advantageously be made of a band gap reference.

Semiconductor memory with voltage stabilization

A charge-coupled memory of the SPS type, in which the input of the series input register is coupled so as to be switchable to an n-bit shift register. The data can thus be read in directly or with a certain delay via the shift register. If an uninterrupted flow of bits is supplied, for example video information, a pause, during which no bits appear at the input of the input register, can be obtained by switching on the shift register in the supply of information to the input register, without information being lost. This pause can be utilized to transport information already read in to the parallel section. As a result, a matrix organization can be given to the memory, in which event the dissipation is lower, the transfer losses are smaller and at the same time a gain in surface area is obtained.

In CMOS integrated circuits, 'latch-up' problems may arise if no special steps are taken. One way to counteract a 'latch-up' state is to apply a substrate bias voltage. In an integrated circuit, an externally-clocked substrate bias voltage pump and a stand-by bias voltage generator are provided, the latter not being switched on until the substrate bias voltage becomes less negative than, for example, -2V. As a result, the integrated circuit becomes less sensitive to 'latch-up', especially during measuring and testing procedures, in which no external clock signal is supplied.

Integrated CMOS circuit comprising a substrate bias voltage generator

An 'Integrated Injection Logic' integrated circuit in which bias currents are supplied by means of a current injector. The current injector is a multi-layer structure in which current is supplied by means of injection and collection of charge carriers via rectifying junctions, to predetermined zones of the circuit to be biased. Such zones are preferably biased by charge carriers which are collected by such zones from one of the layers of the current injector. The circuit also preferably includes a region for reducing carrier injection from a predetermined zone.

Integrated injection logic circuits

A series/parallel/series shift register memory comprises a substrate on which there are provided storage positions for multivalent data elements. There is provided a redundancy generator for generating one or more redundant code elements on the basis of a group of data elements, said redundant code elements being applied to the series input of the shift register memory later than the associated data elements. The code elements are conducted through parallel-connected storage registers which are shorter than those used for the associated data elements, so that a redundancy reducer receives the redundant code elements from a series output before the associated data elements appear on this series output. The reduction of the storage registers, expressed in periods of the shift drive, can be performed in different ways from a technological point of view.

Series/parallel/series shift register memory comprising redundant

A blowable fuse is provided over a part of its length separately from the walls of an enveloping cavity and separated from a supporting member. As a result of this the fuse is readily thermally isolated so that it fuses more rapidly and with less energy. In addition, a semiconductor circuit element, for example a Schottky diode, can be realized below a bridging part of a conductor which serves as an upper wall of the cavity, which results in a high bit density.

Method of manufacturing programmable semiconductor device

A programmable semiconductor device having a microswitch (11) which over a part of its length is provided separately from a bridging conductor (10), for example, a word line and a supporting element. Since the dimensions of the switch (11) and the conductor (10) are independent of each other, the resistance of the conductor (10) may be low so that programmable memories having a high read-in and read-out rate are obtained. In addition the circuit element, for example a Schottky diode (3, 8) can be realized below the bridging part (12) of the conductor (10), which results in a high bit density. Since the switch (11) is present below the conductor (10) the assembly can be passivated in the unprogrammed state by means of a protective layer (20), so that the switch 11 is encapsulated in a hollow space (21).

Programmable semiconductor device and method of manufacturing same

A synchronization system for two active functional units which are interconnected by means of a synchronization connection. In order to obtain reliable synchronization without using an untoward number of wires in the connection, at least one of the two functional units has a generator which is capable of generating three successive discrete signal levels on a single connection wire of the synchronization connection. This function unit also has a detector for detecting a signal transition which is produced by a generator in the other active functional unit and for generating an activation signal in reaction thereto. In response to this activation signal, the generator of the same functional unit produces a succession of two signal transitions from one prevailing extreme signal level to the other extreme signal level of the three successive signal levels. The other functional unit has a detector which produces, in response to the second signal transition of the succession, an activation signal for the generator of the other functional unit in order to produce a synchronized signal transition or transitions. Such successions of signal transitions can be transmitted in one or both directions; the synchronization connection may even consist of a single connection wire on which a total of five different signal levels may then occur.

System comprising mutually synchronizing first and second active

A semiconductor device includes a silicon substrate having an insulating layer with a window. A silicon layer is deposited on the insulating layer and on the silicon substrate surface in the window. This silicon layer has n-type and p-type conductive layer parts which adjoin each other within the window and which each serve as both a connection conductor and an electrode of an active zone of the device. Semiconductor devices in accordance with the invention feature very small surface areas, and are thus particularly suitable for high frequency operation.

Semiconductor device and method of manufacturing same

Semiconductor device having non-metallic connection zones

An integrated circuit memory array having a plurality of memory cells including two cross-coupled transistors of one conductivity type, load transistors of the other conductivity type, and a bit line, connected to the base region of one of the cross-coupled transistors through a bit line transistor. The array features a common node, directly interconnecting all of the base regions of the load transistors and the emitter regions of the cross-coupled transistors, for each of the memory cells; and a row selection line connected to the emitter regions of the load transistors in an associated row of memory cells.

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Eindhoven, Netherlands

Arie Slob