Marvellworld Trade Ltd.

Marvell International Limited

Qlogic Corporation

Arie L Krantz

Kha Nguyen

Gregory T Elkins

A storage controller including a processor and a memory controller. The processor is configured to generate a command corresponding to a first write operation and a second write operation, in which the first write operation is contiguous to the second write operation, and the first write operation is received prior to the second write operation. The command arranges the second write operation prior to the first write operation. The memory controller is configured to, in response to the command, execute each of the first write operation and the second write operation. The second write operation is executed by the memory controller prior to the first write operation.

Disk controller configured to perform out of order execution of write operations

A controller for a disk drive including a buffer memory controller and a processor. The buffer memory controller is configured to receive a first write operation and a second write operation in a first order, store the first write operation and the second write operation in a buffer memory, and transfer write data corresponding to the first write operation and the second write operation in a second order that is different than the first order in response to a single command. The processor is configured to arrange the first write operation and the second write operation in the second order and issue the single command according to the second order.

A controller for a disk drive includes first memory storing first write operations and second write operations received in a first order. A processor arranges the first write operations and the second write operations in a second order based on respective track sectors associated with the first and the second write operations. The second order is different than the first order. A memory controller transfers write operation data corresponding to the first write operations and the second write operations to a disk formatter in the second order in response to a single command from the processor.

A memory controller for a disk controller comprises a first memory that receives first and second write operations in a first order and that stores the first and second write operations and corresponding write operation data. A second memory stores a corresponding address for each of the write operations, wherein the corresponding addresses identify a location of the write operation data stored in the first memory. Controller logic determines whether the first write operation and the second write operation write data to a same track of a disk and transfers the write operation data from the first memory to a third memory in a second order when the first write operation and the second write operation write data to the same track, wherein the second order is different from the first order.

A buffer memory controller comprises a first memory configured to buffer write operation data between a write head and a second memory that stores write operation data corresponding to first and second write operations. A first memory location identifies a location of write operation data that corresponds to the first write operation stored within the second memory. A second memory location identifies a location of write operation data that corresponds to the second write operation stored within the second memory. Controller logic determines whether the first write operation and the second write operation write data to the same track. The controller logic transfers the data of the first write operation and the second write operation in an order other than the order in which the second memory received the first and second write operations when the first write operation and the second write operation write data to the same track.

A hard disk unit includes a disk, controller microprocessor, host bus interface, buffer memory, buffer memory controller and disk formatter. The bus interface receives write operations, and the corresponding write operation data is stored in the buffer memory. The buffer memory controller also includes a set of address registers and a set of block count registers. The microprocessor loads the address registers with the buffer memory addresses of data of multiple write operations and loads the block count registers with the size of the corresponding data. The microprocessor then issues a single command to the buffer memory controller to transfer the data from the buffer memory to the disk formatter. The address registers and block count registers enable the data of multiple write operations to be transferred and written to a disk in an order other than the order in which the write operations were received at the bus interface.

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Mission Viejo, CA, United States of America

Arie L Krantz