Intel Corporation

Arghya Sain

Sujit Sharan

Lijiang Wang

Johanna M Swan

Aleksandar Aleksov

Feras Eid

Robert L Sankman

Henning Braunisch

Kristof Darmawikarta

Kemal Aygun

Sanka Ganesan

Andrew Paul Collins

Jianyong Xie

Sri Chaitra Jyotsna Chavali

Xiaohong Jiang

Arnab Sarkar

Cemil S Geyik

Prashant D Parmar

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

Package design scheme for enabling high-speed low-loss signaling and mitigation of manufacturing risk and cost

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.

Scalable high speed high bandwidth IO signaling package architecture and method of making

Embodiments disclosed herein include electronic packages with improved differential signaling architectures. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises alternating metal layers and dielectric layers. In an embodiment, a first trace is embedded in the package substrate, where the first trace has a first thickness that extends from a first metal layer to a second metal layer. In an embodiment, the electronic package further comprises a first ground plane laterally adjacent to a first side of the first trace, and a second ground plane laterally adjacent to a second side of the first trace.

Variable in-plane signal to ground reference configurations

Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

Via architecture for increased density interface

Growing community of inventors

Chandler, AZ, United States of America

Arghya Sain