Qualcomm Incorporated

Broadcom Corporation

Ardavan Moassessi

Paul Penzes

David Anthony Kidd

Yi Lou

A flip-flop is provided that includes a master latch clocked according to a first delay during a normal mode of operation and clocked by a smaller second delay during a scan mode of operation.

High-speed flip-flop with robust scan-in path hold time

System and methods for forming an integrated circuit using a standard cell library are provided. In some aspects, a method includes arranging cells from the standard cell library into a row between upper and lower power rails. Each cell includes a plurality of lateral nodes, at least one boundary region, and at least one dummy transistor. The method includes identifying a connection pattern of adjacent ones of the cells. The connection pattern is between (i) the lateral nodes of the adjacent cells and (ii) the upper and lower power rails. The method includes removing adjacent boundary regions of the adjacent cells based on the identified connection pattern of the adjacent cells, and modifying an arrangement of adjacent dummy transistors of the adjacent cells based on the removal of the adjacent boundary regions.

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Laguna Niguel, CA, United States of America

Ardavan Moassessi