Maxim Integrated Products, Inc.

Cypress Semiconductor Corporation

Arda Kamil Bafra

Levent Yakay

Mustafa Ertugrul Oner

Caglar Yilmazer

Can Bilgin

Yalcin Balcioglu

Gregory Richmond

Umut Yilmazer

Aysel Yildiz

Described herein are systems and methods that provide for implement an asymmetric image splitter engine that may reduce the memory requirements. In one or more embodiments, a method may comprise receiving a multi-streaming video comprising super-frame video images, where each super-frame video images includes a first video image and a second video image, and where the height of the first video image is higher than the second video image. The vertical asymmetry of the second video image may be adjusted to same height as the first video image by adding padding to the second video image. An asymmetric image splitter engine may be utilized to split the super-frame video images into two separate video images. By marking each line of the second video image, it may be determined which lines are padded and discarded, and which lines are data to be displayed using a line mark memory.

Systems and methods for asymmetric image splitter with line mark memory

A configurable transceiver includes a first transmitter, an edge rate controller, a second transmitter, a subtractor, a bandwidth controller and a main controller. The first transmitter is configured to generate a first signal for transmission via a transmission link. The second transmitter is configured to generate a replica signal associated with the first signal. The edge rate controller is communicatively coupled to the first and/or second transmitter and is configured to control an edge rate parameter of the first and/or second signal. The subtractor is configured to subtract the replica signal from a signal received via the transmission link. The bandwidth controller is configured to control a bandwidth parameter of a difference signal received from the output of the subtractor. The main controller chooses edge rate and bandwidth control words per desired link rates. It can also automatically find the maximum possible link speed.

Configurable bidirectional transceiver for full-duplex serial link communication system

A system for at least substantially plesiochronously operating a receiver in communication with a plurality of cameras (e.g., at least two plesiochronously operational cameras) is described. In one or more implementations, the system includes a plurality of cameras. Each camera is configured to generate a signal for transmission via a communications link, and the signal comprises data packets encoded in a forward channel. The system also includes a receiver communicatively coupled to the plurality of cameras via the single-ended communications link. The receiver is configured to generate a synchronization data based upon at least one of the data packets. The receiver is also configured to modulate the signal to encode the synchronization data in a reverse channel so that the signal comprises the forward channel data and the reverse channel data simultaneously.

Multiple camera synchronization system

A method for assessing link quality includes detecting an eye opening of a transmission link. The detected eye opening of the transmission link is compared with a threshold eye opening or at least one previously detected eye opening. A link quality of the transmission link is assessed based upon a comparison of the eye opening with the threshold eye opening or the at least one previously detected eye opening.

System and method for wide-band adaptive equalization and eye opening monitoring with link quality detection

An apparatus for generating a spread-spectrum signal based on an input signal whose frequency may vary substantially. The apparatus is particularly suited for controlling the frequency of the modulation in response to wide variations of the frequency of the input signal. This prevents the modulation frequency from deviating into an undesired frequency range which could cause adverse operational effects. The apparatus includes a detector adapted to generate a first signal related to the frequency of the input signal, a controller adapted to generate a second signal for controlling a frequency of a modulation signal based on the first signal, a modulation signal generator adapted to generate the modulation signal based on the second signal, and a spread-spectrum signal generator adapted to generate the spread-spectrum signal based on the modulation signal.

System and method of controlling modulation frequency of spread-spectrum signal

System and method for transmitting video and audio data words via a serial data link. A transmitting device includes a first module for generating an audio data frame comprising an audio data word and a frame separation code; and a second module for generating high speed data frames each comprising at least a portion of a video data word and only a portion of the audio data frame, and for transmitting the high speed data frames via the serial data link. A receiving device includes a first module for forming the video data word from one or more high speed data frames, and a second module for forming the audio data frame from portions of high speed data frames. The second module may extract the audio data word from the audio data frame, and generate an audio clock based on a rate in which audio data words are received.

System and method for transmitting audio data over serial link

An apparatus that includes a module for controlling the frequency of a voltage controlled oscillator (VCO) as part of a phase locked loop (PLL), or clock and data recovery (CDR) when an input reference signal to the PLL or serial data to the CDR has ceased from being received. In particular, the apparatus comprises a VCO adapted to generate a VCO clock signal, a first control module adapted to control the frequency of the VCO clock signal based on the input reference signal, and a second control module adapted to control the frequency of the VCO clock signal in response to an absence of the input reference signal. By controlling the frequency of the VCO clock signal during an absence of the input reference signal, the first control module is able to more easily re-acquire control the frequency of the VCO clock signal when the input reference signal is received again.

System and method for automatic leakage control circuit for clock/data recovery and charge-pump phase locked loops

A method and circuit for performing switching in a frequency timing generator is described. The method includes detecting a request for a new value for a feedback counter or an reference counter, upon which a loading operation is synchronized for the appropriate counter. A time-out order of the feedback counter and the reference counter is determined. Where no time-out order difference is detected therein, a state machine status word function is completed. Where a time-out order difference is detected therein, it is determined which of the reference counter and the feedback counter times out first. Where the reference counter times out first, a constant charge pump current is delivered to a loop filter associated with a phase locked loop to achieve an upward frequency direction. Where the feedback counter times out first, a constant charge pump current is delivered to the loop filter to achieve a downward frequency direction.

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Istanbul, Turkey

Arda Kamil Bafra