Unisys Corporation

Sperry Corporation

Archie E Lahti

Larry L Byers

John T Rusterholz

Kenneth L Engelbrecht

James R Hamstra

Michael Danilenko

Louis B Bushard

Charles J Homan

Donald R Kalvestrand

Ralph L James

A vector file organization for a multiple pipelined vector processor with data transfer capability to support multiple program execution pipelines. Multiple pipelines can simultaneously access various blocks of the vector file through segmenting the file storage and by addressing the various elements of the segments. Vector files of programmable registers each have storage for sixty-four elements of 36-bit words or thirty-two elements of 64-bit words. Six independent execution pipelines in combination can programmably access the vector files for either read operands or write operands or both. Each vector file has N independent blocks, each using a RAM with read output to the pipelines, an address register and a write data register. Each block holds interspersed word pairs of words of each vector file. Primary and secondary vector files are equal in capability and allow reading pairs of elements, as required by arithmetic instructions. Shadow storage similarly arranged and addressed provides storage for intermediate result vectors. A time slot management mechanism uses N registers connected in serial loop, to allocate and reserve access to the vector files by the execution pipe for each instruction execution to maintain its function. It forms a read or write address for both the primary and secondary files and references all N blocks in a pass.

Scientific processor vector file organization

An improved Scientific Processor for use in a data processing system having a general purpose host processor and a High Performance Storage Unit, and under operational control of the host processor is described. The Scientific Processor includes a Vector Processor Module and a Scalar Processor Module, each operable at comparable rates, wherein scalar operands and vector operands can be manipulated in various combinations under program control of an associated host processor, all without requirement of dedicated storage or caching. The Scalar Processor Module includes instruction flow control circuitry, loop control circuitry for controlling nested loops, and addressing circuitry for generating addresses to be referenced in the High Performance Storage Unit. A scalar processor arithmetic logic unit is described for performing scalar manipulations. The Vector Processor Module includes vector control circuitry and vector file storage circuitry together with vector file loading and vector storage circuitry. A plurality of vector manipulating pipelines for performing instruction functions of vector addition, vector multiplication and vector move is described wherein the pipelined functions can occur simultaneously, and each pipeline is capable of providing resultant operand pairs at a rate approximately equal to the reference cycle of the High Performance Storage Unit.

Scientific processor to support a host processor referencing common

A system for controlling an activity (program) switch on a scientific processor having an external executive control program. It includes the sequencing of the hardware at a macro level rather than at the more detailed lower levels previously used. This sequencing and control is accomplished by providing a macro code control, a macro code store and an instruction buffer write data selector interconnected with the existing macro logic and the main storage of the scientific processor to provide a system for starting, running and stopping the scientific processor by an activity switch which responds to interrupt signals to selectively shift from the receipt of data from the main storage to the receipt of data from the macro code store.

Macro level control of an activity switch in a scientific vector

A system for detecting and resolving logical usage conflicts is described for use in a scientific data processing system. A plurality of pipelined overlapping macro instructions request access to the system memory. Often the information required by a subsequent instruction is not available until an earlier overlapped instruction has been completed thereby creating a conflict. This conflict is sensed by the subsequent instruction and memory access is delayed a number of memory cycles until the correct information is available at which time the subsequent instruction is allowed to proceed. This allows a scientific vector support processor having a high degree of asynchronism to be able to produce results as if no overlap existed to provide program execution results as if each instruction were executed serially to completion in the proper program order. There are three categories of data logical usage conflicts. First, a Write/Read conflicts occurs where there is an attempt to read a result vector element of an earlier instruction before the result vector is written. Next, a Read/Write conflict occurs when there is an attempt to overwrite a source vector element of an earlier instruction before it has been read. Finally, a Write/Write conflict occurs where there is an attempt to overwrite a result vector element of an earlier instruction before it is written.

Vector data logical usage conflict detection

A first load vector instruction signal V1 is read from an instruction buffer into an instruction read register. V1 is decoded and routed simultaneously to scalar and vector processor instruction issue registers. V1 is next routed to a vector instruction stage register and from there to a vector load execution pipe. A second load vector instruction signal V2 proceeds in a similar manner until it reaches the vector instruction stage register and is held there because the vector load execution pipe is busy with V1. A store vector instruction signal S1 proceeds in a similar manner until it reaches the vector processor instruction issue register. S1 cannot proceed further as V2 is queued in the vector instruction stage register. A bypass mechanism includes a bypass test register, a bypassed instruction hold register and a bypass control and sequence logic. S1 is transferred into the bypass test register at each clock cycle. The bypass control and sequence logic initiates a bypass sequence. Under the control of the bypass control and sequence logic, V2 is transferred from the vector instruction stage register to the bypassed instruction hold register. S1 is allowed to proceed to the vector instruction stage register and then on to a vector store execution pipe. V2 is returned to the vector instruction stage register completing the bypass sequence.

Apparatus for out-of-order program execution

A method and a means of increasing the performance of an instruction buffer in a digital data processing system is disclosed. The improvement is accomplished by by-passing the content addressable memory operation which has heretofore been utilized to access page addresses in the instruction buffer. As each word included on the same page was accessed, the CAM was repetitiously activated even though it was accessing the same page. In the present system, word accesses made to the same page are handled in a much improved manner. In the present system, a comparator is implemented in the system which compares the presently reference page with the previously referenced word, so that when a match is noted, i.e., the same page is indicated, the CAM is bypassed and successive requests made to the same page are satisfied from the instruction buffer by a validity designator which designates that the presently referenced word is the correct one.

Instruction buffer for a digital data processing system

A system for overlapping macro instruction execution is described for use in a data processing system. A pair of control storage devices each store the micro instruction sets required to execute all macro instructions in the repertoire and are used for alternate macro instructions. Each of the controlled storage devices is addressable to entry addresses by the macro instructions. After entry, addressing is by the contents of the micro instructions with provision made for conditional branching. An overlap count storage device is provided for storing overlap counts for all possible sequences of macro instructions. These overlap counts define the number of micro instructions of the current macro instruction that must be executed before the next macro instruction can proceed. Micro instruction execution is by clock cycle and are counted as they are executed. The count is compared to the stored overlap count for the current sequence of macro instructions and overlap execution is enabled when comparison is found. Overlap of macro instruction execution is allowed to occur when the current remaining micro instructions for the current macro instruction define functions that are mutually exclusive with the functions controlled by the next macro instruction. During overlap, micro instructions are loaded in an execution register from both control storage devices. Overlapping instructions that have variable execution sequences is controlled by halting the count of micro instruction executions until the variable sequence has been completed.

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Fridley, MN, United States of America

Archie E Lahti