Tanisys Technology, Inc.

King Tiger Technology, Inc.

Archer R Lawrence

Jack C Little

Paul R Hunter

Robert A Barr

Michael S West

Brian Kleen

Joseph C Klein

Allen Jett

Electronic devices, such as memory devices are tested by applying test data, such as vectors of memory data having data field, control and address information, with a tester to detect error responses. Applied test data is captured, compressed and stored for subsequent analysis to isolate the test data associated with the error response. The saved compressed test data is de-compressed to replay the test data for a logic analyzer so that adequate history of the test data exists to determine the test cycles that included the stimulus associated with the error response. Identification of the test cycles that include the stimulus associated with the error response allows creation of test programs that run in reduced time by avoiding empty test cycles not associated with the error response.

Method and system for test data capture and compression for electronic device analysis

A distributed tester method and system communicates test recipes for testing electronic devices from a host computer over a network to a test site. The test site translates test recipes into test instructions for execution by a test engine that determines the status of the electronic device. For instance, in a tester for testing memory, a test recipe is defined and stored with a host computer to determine test data for storage on the memory device under test at the test site. The host computer controls execution of the test recipe over the network. The test recipe is defined and stored in an XML formatted data file transmitted over the network to a processor at the test site. The test site processor translates the XML formatted data into test instructions for execution by a test engine. The test engine determines whether the memory device under test accurately stores data and provides the results, such as erroneously stored data, to the host computer through the network. A test design host and a global data master also interface with the network to aid the design and storage of test recipes. The distributed test method and system advantageously improves flexibility of testing over a geographically disbursed area and with divergent test recipes and devices under test.

Method and system for distributed testing of electronic devices

A time conserving method of identifying width, depth, access time, control line configurations, and part type of any of a plurality of different synchronous memories. A nested loop process is used to develop, and apply to a synchronous memory being identified, trial control line configurations taken from ordered entries of tables representative of the plurality of synchronous memories. The width, depth, control line configurations, and part type are determined from the responses evoked from the synchronous memory being identified. The delay between a read command issued by the test system CPU and a reading of bit patterns from the synchronous memory is incremented in finite steps in successive write/read iterations until the bit pattern read is identified to the bit pattern written into the synchronous memory, thereby identifying the access time of the synchronous memory.

Method and system for automatic synchronous memory identification

A digital programmable delay which provides a series of pulses that are programmed in both pulse latency and trigger latency to control the operation of a memory module test system.

Programmable pulse generator

A tester for use with a device under test includes a processor, a signal timing editor to create representations of signal waveforms and associated times, and a test program executable on the processor that schedules events based on information from the signal timing editor. The test program schedules different delays for the events to compensate for variations in time delays between different signals coupled to the device under test.

Tester systems

A system and method for reducing voltage stabilization time in a leakage current test system, and thereby reducing the time for measuring leakage currents in the I/O pins of an IC chip including CMOS DRAMs is disclosed. The method and system of the present invention accelerates leakage current testing time by precharging the capacitance of the I/O pins under test to a voltage near the settled voltage level, before measuring leakage current at the I/O pin contact points of packaged IC chips and assembled IC modules, and indicating when an I/O pin is defective.

Parametric test system and method

An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, board or module, without requiring hardware modifications or additions to the memory device being identified, and without requiring storage of test patterns or characterizing, data in the memory device.

Synchronous memory test system

An automated, portable, and time conservative memory test system for identifying test parameters including type, control line configuration, depth, width, access time, and burst features of any one of a wide variety of synchronous memories including SDRAMs and SGRAMs, and whether an IC chip, bank, board or module, without requiring hardware modifications or additions to the memory device being identified, and without requiring storage of test patterns or characterizing data in the memory device.

Synchronous memory tester

Synchronous memory test method

A nested loop method for use in a memory test system to identify the width, depth, control line configuration, and part type of a synchronous memory, wherein bit patterns are retrieved from tables representative of a plurality of synchronous memories during execution of nested loops, from outer loop to inner loop, in the order of bank loop, RE loop, CE loop, CS loop, DQMB loop, and part type loop, and bits of an entry of a table occurring after a given entry are either a member of a superset or do not intersect bits of previous entries, and bits of an entry preceding the given entry are either a member of a subset or do not intersect bits of the given entry.

Growing community of inventors

Austin, TX, United States of America

Archer R Lawrence