Texas Instruments Corporation

Archana Venugopal

Luigi Colombo

Benjamin Stassen Cook

Nazila Dadvand

Robert R Doering

Marie Denison

Arup Polley

Sameer P Pendharkar

Henry Litzmann Edwards

John Anthony Rodriguez

Joseph Maurice Khayat

Daniel Lee Revier

Darvin R Edwards

Richard Allen Bailey

Dhishan Kande

Hiep Xuan Nguyen

Michael Allen Ball

Sunil Kumar Dusa

Jingjing Chen

Robert Reid Doering

An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

High voltage avalanche diode for active clamp drivers

A microelectronic device including a substrate having a semiconductor material containing an embedded thermoelectric cooler with thermally anisotropic mesas between the cold terminal and the hot terminal of the embedded thermoelectric cooler adjacent to a heat source; the adjacent embedded thermoelectric cooler providing a temperature reduction for the heat source resulting in increased safe operating area (SOA) for the microelectronic device. The thermally anisotropic mesas are formed in parallel with deep trenches used as isolation in the microelectronic device.

Embedded thermoelectric cooler using thermally anisotropic mesas for power device heat generating source temperature reduction

A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.

Filler particles for polymers

An integrated circuit has a substrate that includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

Thermal routing trench by additive processing

A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.

-bonded carbon structures

In described examples, a semiconductor wafer with a thermally conductive surface layer comprises a bulk semiconductor layer having a first surface and a second surface, circuitry on the first surface, a metallic layer attached to the first surface or the second surface, and a graphene layer attached to the metallic layer. The first surface opposes the second surface. The metallic layer comprises a transition metal.

Thermally conductive wafer layer

An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

High thermal conductivity vias by additive processing

A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice. A ceramic may be deposited on the graphene and another graphene layer may be deposited on top of the ceramic to create a multi-layered sp-bonded carbon tube.

Multi-layered SP-bonded carbon tubes

A microstructure comprises a plurality of interconnected units wherein the units are formed of hexagonal boron nitride (h-BN) tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing an h-BN precursor on the metal microlattice, converting the h-BN precursor to h-BN, and removing the metal microlattice.

Hexagonal boron nitride structures

In described examples, a circuit (e.g., an integrated circuit) includes a semiconductor substrate that includes a frontside surface and a backside surface. A circuit element is included at the frontside surface. An optional electrical insulator layer can be included adjacent to the backside surface. A distributor layer is included adjacent to the backside surface. In some examples, the distributor layer includes a distributor material that includes a matrix of cohered nanoparticles and metallic particles embedded by the cohered nanoparticles.

Nanoparticle matrix for backside heat spreading

A switchable array includes: a microstructure of interconnected units formed of graphene tubes with open spaces in the microstructure bounded by the graphene tubes; at least one JFET gate in at least one of the graphene tubes; and a control line having an end connected to the at least one JFET gate. The control line extends to a periphery of the microstructure.

Multi-super lattice for switchable arrays

A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.

Integration of graphene and boron nitride hetero-structure device over semiconductor layer

A composite material comprises a polymer matrix having microstructure filler materials that comprise a plurality of interconnected units wherein the units are formed of connected tubes. The tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, growing or depositing a material on the metal microlattice such as graphene, hexagonal boron nitride or other ceramic, and subsequently removing the metal microlattice.

An interconnect structure for a semiconductor device includes a plurality of unit cells. Each unit cell is formed of interconnected conducting segments. The plurality of unit cells forms a conducting lattice.

Growing community of inventors

Dallas, TX, United States of America

Archana Venugopal