Intel Corporation

Nvidia Corporation

Aravindh Baktha

Per H Hammarlund

Ks Venkatraman

Stephan Jourdan

Guillermo Juan Rozas

David A Dunn

Alexander Klaiber

Darrell D Boggs

Herbert H Hum

Paul S Serris

Michael D Upton

Ross Segelken

Sebastien Hily

Hermann Gartler

Magnus Ekman

James Van Zoeren

Zhongying Zhang

Hens Vanderschoot

Brad Hoyt

Sridharan Ramakrishnan

Harish Kumar

Mike D Upton

Venkat K S Venkatraman

Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic.

Queued instruction re-dispatch after runahead

Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.

Apparatus and method for store address for store address prefetch and line locking

A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may be compared with the context identifier in the cache line's tag. The cache line's data block may be transferred if the context identifiers and the tags match.

Use of a context identifier in a cache memory

A method and apparatus for whacking a &#x3bc;OP based upon the criticality of that &#x3bc;OP. Also disclosed are embodiments of a method for determining the criticality of a &#x3bc;OP.

Placing front instruction in replay loop to front to place side instruction into execution stream upon determination of criticality

A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences associated with multiple threads of a processing device.

Method and apparatus for handling locks

Growing community of inventors

Portland, OR, United States of America

Aravindh Baktha