Intel Corporation

Cornell Research Foundation Inc.

Aravind S Killampalli

Jay P Gupta

Prashant Majhi

Tahir Ghani

Anand S Murthy

Glenn A Glass

Harold W Kennel

Jack Hwang

Sridhar Govindaraju

Karson Knutson

Mark R Brazier

Jaya P Gupta

Jack T Kavalieros

Gilbert W Dewey

Ravi Pillarisetty

Willy Rachmady

Niloy Mukherjee

Uday Shah

James S Clarke

Charles Henry Wallace

Elijah V Karpov

Bernhard Sell

Cheng-Ying Huang

Paul F Ma

Jeanne Luce

James R Engstrom

Ebony L Mays

Pulkit Jain

Byungki Jung

Prashant Wadhwa

Chad Byers

Justin Railsback

Supanee Sukrittanon

Caleb Barrett

Nishant Gupta

Jonathan E Leonard

Kaiwen Hsu

Transistor structures including a non-planar body that has an active portion comprising a semiconductor material of a first height that is variable, and an inactive portion comprising an oxide of the semiconductor material of a second variable height, complementary to the first height. Gate electrodes and source/drain terminals may be coupled through a transistor channel having any width that varies according to the first height. Oxidation of a semiconductor material may be selectively catalyzed to convert a desired portion of a non-planar body into the oxide of the semiconductor material. Oxidation may be enhanced through the application of a catalyst, such as one comprising metal and oxygen, for example.

Transistor structures including a non-planar body having variable and complementary semiconductor and insulator portions

A high-pressure dielectric film curing apparatus, such as a high-pressure batch furnace, is controlled to an elevated cure temperature and super-atmospheric pressure for the duration of the film curing time with the cure pressure achieved at least partially with a vapor of aqueous ammonia in fluid communication with the chamber. The cure temperature may vary, for example between 175&#xb0; C., and 400&#xb0; C., or more. The cure pressure may also vary as limited by the saturated water vapor pressure, for example between 100 PSIA and 300 PSIA, or more. The aqueous ammonia may be injected into the chamber or vaporized upstream of the chamber. One or more carrier and/or diluent gas (vapor) may be introduced into the chamber to adjust the partial pressure of ammonia vapor, water vapor, and the diluent.

Method and apparatus for high pressure cure of flowable dielectric films

Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

Deuterium-based passivation of non-planar transistor interfaces

A flowable chemical vapor deposition method including depositing a dielectric film precursor on a substrate in a flowable form; depositing an oligomerization agent on the substrate; forming a dielectric film from the dielectric film precursor; and curing the dielectric film under a pressure greater than atmospheric pressure. A method including depositing a dielectric film precursor as a liquid on a substrate in the presence of an oligomerization agent; treating the deposited dielectric film precursor to inhibit outgassing; and curing the dielectric film precursor to form a dielectric film. A method including delivering a dielectric film precursor as a vapor to a substrate including gap structures between device features; condensing the dielectric film precursor on the substrate to a liquid; flowing the liquid into the gap structures; and curing the dielectric film precursor under a pressure of 15 pounds per square inch gauge or greater.

Dielectric gap-fill material deposition

An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; and an oxide layer between the OEL and the bottom electrode; wherein the oxide layer includes Deuterium and oxygen vacancies. Other embodiments are described herein.

Resistive random access memory with deuterium

Techniques are disclosed for sub-second annealing a lithographic feature to, for example, tailor or otherwise selectively alter its profile in one, two, or three dimensions. Alternatively, or in addition to, the techniques can be used, for example, to smooth or otherwise reduce photoresist line width/edge roughness and/or to reduce defect density. In some cases, the sub-second annealing process has a time-temperature profile that can effectively change the magnitude of resist shrinkage in one or more dimensions or otherwise modify the resist in a desired way (e.g., smooth the resist). The techniques may be implemented, for example, with any type of photoresist (e.g., organic, inorganic, hybrid, molecular photoresist materials) and can be used in forming, for instance, processor microarchitectures, memory circuitry, logic arrays, and numerous other digital/analog/hybrid integrated semiconductor devices.

Sub-second annealing lithography techniques

An annealing method and apparatus for semiconductor manufacturing is described. The method and apparatus allows an anneal that can span a thermal budget and be tailored to a specific process and its corresponding activation energy. In some cases, the annealing method spans a timeframe from about 1 millisecond to about 1 second. An example for this annealing method includes a sub-second anneal method where a reduction in the formation of nickel pipes is achieved during salicide processing. In some cases, the method and apparatus combine the rapid heating rate of a sub-second anneal with a thermally conductive substrate to provide quick cooling for a silicon wafer. Thus, the thermal budget of the sub-second anneal methods may span the range from conventional RTP anneals to flash annealing processes (including duration of the anneal, as well as peak temperature). Other embodiments are described.

Sub-second annealing processes for semiconductor devices

Systems and methods for preparing inorganic-organic interfaces using organo-transition metal complexes and self-assembled monolayers as organic surfaces. In one embodiment, a silicon wafer is cleaned and reacted with stabilized pirhana etch to provide an oxide surface. The surface is reacted with the trichlorosilyl end of alkyltrichlorosilanes to prepare self assembling monomers (SAMs). The alkyltrichlorosilanes have the general formula R1-R&#x2014;SiCl, where R1 is &#x2014;OH, &#x2014;NH, &#x2014;COOH, &#x2014;SH, COOCH, &#x2014;CN, and R is a conjugated hydrocarbon, such as (CH2)where n is in the range of 3 to 18. The functionalized end of the SAM can optionally modified chemically as appropriate, and is then reacted with metal-bearing species such as tetrakis(dimethylamido)titanium, Ti[N(CH)], (TDMAT) to provide a titanium nitride layer.

Growth of inorganic thin films using self-assembled monolayers as nucleation sites

Temperature measurement using a pyrometer in a processing chamber is described. The extraneous light received by the pyrometer is reduced. In one example, a photodetector is used to measure the intensity of light within the processing chamber at a defined wavelength. A temperature circuit is used to convert the measured light intensity to a temperature signal, and a doped optical window between a heat source and a workpiece inside processing chamber is used to absorb light at the defined wavelength directed at the workpiece from the heat source.

Temperature measurement with reduced extraneous infrared in a processing chamber

Growing community of inventors

Beaverton, OR, United States of America

Aravind S Killampalli