Texas Instruments Corporation

Aravind Chennimalai Appaswamy

Farzan Farbiz

Akram Ali Salman

James Paul Di Sarro

Ann Margaret Concannon

Gianluca Boselli

Mariano Dissegna

John Eric Kunz, Jr

Krishna Praveen Mysore Rajagopal

Yang Xiu

Stanley Phillips

Muhammad Yusuf Ali

Rajkumar Sankaralingam

Zaichen Chen

Vishwanath Joshi

James Paul DiSarro

Jofin Joseph Vadakkeparasseril

A semiconductor device is described herein. The semiconductor device includes a substrate and a collector region in the substrate. The semiconductor device also includes a plurality of emitter regions in the substrate, each of the plurality emitter regions separate from each other, wherein the plurality of emitter regions is disposed in an area bounded by the collector region.

Repeated emitter design for achieving scalable lateral PNP behavior

An electrostatic discharge protection system with a node adapted to receive a signal and threshold detecting circuitry coupled to the node. The system includes an IGBT having an IGBT gate coupled to an output of the threshold detecting circuitry, a resistor coupled between an IGBT emitter of the IGBT and a low reference potential node, and a BJT having a BJT base coupled to the IGBT emitter.

Compact area electrostatic discharge protection circuit

An SCR with a first semiconductor region and plural concentric semiconductor regions, each surrounding the first semiconductor region. The SCR also includes, surrounded by at least one concentric semiconductor region in the plurality of concentric semiconductor regions, an electrically non-contacted region of a semiconductor type and positioned to modulate a snapback voltage of the silicon controlled rectifier and an electrically-contacted region of the semiconductor type and positioned to provide a diodic response between the at least one concentric semiconductor region in the plurality of concentric semiconductor regions and the electrically-contacted region.

Lateral high voltage SCR with integrated negative strike diode

An electrostatic discharge (ESD) device with fast response to high transient currents. The ESD device includes a short-pulse discharge (SPD) path and a long-pulse discharge (LPD) path. The SPD path provides robust response to ESD events, and it triggers a self-bias configuration of the LPD path. Advantageously, the SPD path reduces the risk of ESD voltage overshoot by promptly discharging short-pulse currents, such as a charge device model (CDM) current, whereas the LPD path provides efficient discharge of long-pulse currents, such as a human body model (HBM) current. In one implementation, for example, the SPD path includes a MOS transistor, and the LPD includes a bipolar transistor having a base coupled to the source of the MOS transistor.

ESD device with fast response and high transient current

An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.

Conductivity modulated drain extended MOSFET

Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.

ESD protection circuit with passive trigger voltage controlled shut-off

According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.

High voltage bipolar structure for improved pulse width scalability

A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.

Electrostatic discharge device

In some examples, an electrostatic discharge (ESD) device comprises an insulated-gate bipolar transistor (IGBT) comprising a source terminal, an anode terminal, a gate terminal, and a body terminal; and at least one reverse bias device comprising a first terminal and a second terminal, wherein the first terminal couples to the source terminal and the second terminal couples to the body terminal.

IGBT coupled to a reverse bias device in series

A silicon controlled rectifier (SCR) using separate bipolar transistors is disclosed. The separate bipolar SCR enables access to internal feedback terminals of the SCR, which may then may be used to adjust the gain of individual bipolar transistors. Further embodiments provide custom design latch up immune solutions. The latch up immunity is achieved by integrating an active Field Effect Transistor (FET) into the internal feedback node of the SCR. This provides access to 'feedback' node of the SCR allowing for latch-up free SCR design. The active FET times out in a short time period (e.g., microseconds) thus shutting off the SCR feedback mechanism making the SCR latch-up immune.

Variable holding voltage silicon controlled rectifier using separate and distinct bipolars

An electrostatic discharge (ESD) protection circuit includes a substrate having a semiconductor surface that the ESD protection circuit formed thereon. A first ESD cell is stacked in series with at least a second ESD cell. An active shunt transistor is electrically in parallel with the first ESD cell or second ESD cell, where the active shunt includes a control node. A trigger circuit has a trigger input and a trigger output, wherein the trigger output is coupled to the control node.

Growing community of inventors

Plano, TX, United States of America

Aravind Chennimalai Appaswamy