Qualcomm Incorporated

Aravind Bhaskara

Tao Shen

Wenbiao Wang

Tauseef Kazi

Stephen A Molloy

Joshua Stubbs

Boris Andreev

Jeffrey Gemar

Vinod Chamarty

Olivier Alavoine

Simon Booth

Edoardo Regini

Renatas Jakushokas

Sejoong Lee

Zhurang Zhao

Jun Liu

Saurabh Patodia

Jayson Roy Smith

Kiran Bhagwat

Michael Tipton

Hengzhou Ding

Narendranath Malayath

Ying Noyes

Haw-Jing Lo

Michael Hawjing Lo

Raghavendra Nagaraj

Sumit Mohan

Ho Sang Lee

Jeffrey Hao Chu

Scott Cheng

Rohan Desai

Wei Zou

Rengaraj Thirupathi

Nishant Hariharan

Yonggui Mao

Jyotirmoy Das

Mohit Bhave

Thomas Tang

Pavan Kumar Chilamkurthi

Systems, methods, and computer-readable media are provided for camera dynamic voting to optimize fast sensor mode power. In some examples, a computing device can obtain, based on performing dynamic voting, a plurality of votes associated with a plurality of components sharing a power source. The computing device can determine a voting result based on the plurality of votes. The computing device can increase or decreasing a clock rate and a voltage for the power source based on the voting result to produce an updated clock rate and an updated voltage. The computing device can then apply the updated clock rate and the updated voltage to an image processor.

Camera dynamic voting to optimize fast sensor mode power

Various dynamic voltage and frequency scaling (DVFS) techniques can optimize the high voltage residency of a device containing multiple processing cores that share a voltage rail. The DVFS techniques described herein can reduce the high voltage residency (duration) of the voltage rail by aligning the high frequency duration of multiple cores sharing the same voltage rail.

Ruler-follower dynamic voltage and frequency scaling schemes for integrated circuit components

Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

Forced idling of memory subsystems

Methods and apparatus to manage image signal processor (ISP) data traffic is provided. The apparatus includes an ISP having an ISP front-end configured to receive image data and a first memory configured to store the image data. The ISP front-end is further configured to output the image data stored in the first memory to a second memory via a memory link in response to the image data stored in the first memory reaching a size threshold. Another apparatus includes apparatus includes a camera sensor configured to output image data in a camera mode, an ISP on a die, a camera link coupling the camera sensor and the ISP, a memory, and a memory link coupling the ISP and the memory. The memory link is configured to enter a low-power mode in the camera mode.

Image signal processor data traffic management

An image capture device that includes an adjustment circuit configured to monitor image parameters, generate updated image settings for the image capture device in response to the monitored image parameters, and transmit the updated image settings to one or more processors. The updated image settings configure the one or more processors to determine whether to transition the image capture device from a dynamic scene mode to a static scene mode based on a first image parameter included in the monitored image parameters, wherein the first image parameter is different from a second image parameter used to determine to transition the image capture device from the static scene mode to the dynamic scene mode, and to suspend generation of all or less than all of the updated image settings in response to determining to transition the image capture device from the dynamic scene mode to the static scene mode.

Power saving techniques for an image capture device

Techniques for intensity compensation in video processing are provided. In one configuration, a wireless communication device compliant with the VC1-SMPTE standard (e.g., cellular phone, etc.) comprises a processor that is configured to execute instructions operative to reconstruct reference frames from a received video bitstream. A non-intensity-compensated copy of a reference frame of the bitstream is stored in a memory of the device and used for defining the displayable images and for on-the-fly generation of a stream of intensity-compensated pixels to perform motion compensation calculations for frames of the video bitstream.

Intensity compensation techniques in video processing

A video stream (for example, H.264 video) includes intra-encoded portions. Decoding an intra-encoded portion utilizes the result of decoding one or more other portions (called predecessors) in the frame. Frame reconstruction involves identifying a portion that has no predecessor portions that have not been decoded and then initiating decoding of the identified portion(s). When the decoding of a portion is substantially complete, then the remaining portions to be decoded are examined to identify portions that have no predecessors that have not been decoded. By carrying out this method, multiple portions may be decoded simultaneously. Each can be decoded on a different work entity, thereby increasing the rate of decoding of the overall frame. Because deblock filtering a predecessor destroys information needed in the intra-decoding of other portions, prefiltered predecessor information is stored in a buffer for subsequent use during intra-decoding, thereby facilitating simultaneous decoding of multiple portions.

Parallel decoding of intra-encoded video

The disclosure describes video decoding techniques that utilize parallel processor technology in order to accelerate the decoding processes of image frames. The techniques include defining batches of video blocks to be decoded in parallel with one another. According to this disclosure, a method may comprise defining a first batch of video blocks of an image frame, decoding the first batch of video blocks in a serial manner, defining a second batch of video blocks and a third batch of video blocks relative to the first batch of video blocks, and decoding the second and third batches of video blocks in parallel with one another.

Parallel batch decoding of video blocks

Growing community of inventors

San Diego, CA, United States of America

Aravind Bhaskara