Texas Instruments Corporation

Arash Loloee

Ismail Hakki Oguzman

Eric G Soenen

Myron J Koen

Ching-Yuh Tsay

Karthik Vasanth

Suribhotla Rajasekhar

An ultrasound transmitter including intrinsic output zeroing is disclosed herein. A transmitter for generating ultrasound signals includes a first transmitter output driver and a first transmitter input driver. The first transmitter output driver includes an N-type device serially coupled to a P-type device. The first transmitter input driver includes an N-type device serially coupled to a P-type device. An output of the first transmitter input driver is coupled to an input of the first transmitter output driver. The first transmitter output driver drives an output of the transmitter to a first voltage and the first transmitter input driver drives the output of the transmitter to a second voltage while the first transmitter output driver is disabled.

High voltage ultrasound transmitter with gate protection diodes and intrinsic output zeroing

A system and method for providing a high voltage ultrasonic drive signal from an ultrasound transmitter are disclosed herein. An ultrasound transmitter includes a first driver and a bias network. The first driver includes a first plurality of drive transistors that when activated drive an ultrasound transmitter output to a first voltage. The first bias network is coupled to the first plurality of drive transistors, and, at least in part, controls distribution, across the drive transistors, of voltage at the ultrasound transmitter output. Control inputs of the first driver are decoupled from the ultrasound transmitter output.

High voltage ultrasound transmitter with symmetrical high and low side drivers comprising stacked transistors and fast discharge

A correlated double sampled/programmable gain amplifier (CDS/PGA) is disclosed which is operable to precondition a CCD output analog signal. The CDS/PGA includes an operational amplifier that is configured in a sample hold operation. The single-ended input is first clamped by a switch ( ) to clamp the DC level therein for a given pixel. A switch ( ) then samples the reset level onto a sampling capacitor ( ), and a switch ( ) thereafter samples the video signal onto one plate of a capacitor ( ). The lower plates of the capacitors ( ) and ( ) are then equalized and the other plates thereof connected to the positive and negative inputs of the operational amplifier ( ). An offset is provided by a programmable DAC ( ) to account for the dark current offset. The output scale is adjusted or mapped by limiting the output between a negative and a positive reference input. The sampling capacitors ( ) and ( ) can be varied to vary the gain of the amplifier.

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Allen, TX, United States of America

Arash Loloee