Sandisk Technologies Inc.

Quswami, Inc.

Leland Stanford Junior University

University of California

Arash Hazeghi

Deepanshu Dutta

Huai-Yuan Tseng

Jawahar M Gidwani

Andrew C Lam

Attila Horvath

Dana Lee

Cynthia Hsu

Navneeth Kankani

H S Philip Wong

Zhenming Zhou

Gerrit Jan Hemink

Henry Chin

Patrick Smith

Bo Lei

Shih-Chung Lee

Ali Javey

Kuniharu Takei

David J K Goldhaber

Yang Chai

Joseph A Sulpizio

An energy conversion device for conversion of chemical energy into electricity. The energy conversion device has a first and second electrode. A substrate is present that has a porous semiconductor or dielectric layer placed thereover. The porous semiconductor or dielectric layer can be a nano-engineered structure. A porous catalyst material is placed on at least a portion of the porous semiconductor or dielectric layer such that at least some of the porous catalyst material enters the nano-engineered structure of the porous semiconductor or dielectric layer, thereby forming an intertwining region.

System and method for converting chemical energy into electrical energy using nano-engineered porous network materials

Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

Multi-die programming with die-jumping induced periodic delays

A method of conductively coupling a carbon nanostructure and a metal electrode is provided that includes disposing a carbon nanostructure on a substrate, depositing a carbon-containing layer on the carbon nanostructure, according to one embodiment, and depositing a metal electrode on the carbon-containing layer. Further provided is a conductively coupled carbon nanostructure device that includes a carbon nanostructure disposed on a substrate, a carbon-containing layer disposed on the carbon nanostructure and a metal electrode disposed on the carbon-containing layer, where a low resistance coupling between the carbon nanostructure and metal elements is provided.

Methods of establishing low-resistance electrical contact to carbon nanostructures with graphitic interfacial layer

A memory device includes memory cells arranged in word lines. Due to variations in the fabrication process, with width and spacing between word lines can vary, resulting in widened threshold voltage distributions. In one approach, a programming parameter is optimized for each word line based on a measurement of the threshold voltage distributions in an initial programming operation. An adjustment to the programming parameter of a word line can be based, e.g., on measurements from adjacent word lines, and a position of the word line in a set of word lines. The programming parameter can include a programming mode such as a number of programming passes. Moreover, the programming parameters from one set of word lines can be used for another set of word lines having a similar physical layout due to the variations in the fabrication process.

Word line dependent programming in a memory device

The present disclosure relates to a nanopillar tunneling photovoltaic ('NPTPV'), and method for fabricating it. The NPTPV device has a regular array of semiconductor pillar cores formed on a substrate having a conductive surface. Layers of high-k material are formed on the cores to provide an efficient tunneling layer for electrons (or holes) generated by incident photons in the cores. Transparent conductive collector layers are formed on the tunneling layer to collect the tunneled carriers. An optimized deposition process, various surface preparations, an interfacial layer between the pillars and the high-k tunnel layer, and optimized pre- and post-deposition annealing reduce the interface trap density and thus reduce recombination prior to tunneling. The absence of a junction also reduces core recombination, resulting in a high short-circuit current. Modifying the collector material and core doping tunes the open-circuit voltage. Such NPTPVs result in large-scale low-cost PVs.

Nanopillar tunneling photovoltaic cell

A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected for sensing. This may be done without body-biasing the NAND string. Having the magnitude of the voltage applied to the source end of a NAND string depend on the location of the selected memory cell (without any body biasing) helps to mitigate failures that are dependent on which word line is selected during a sensing operation of one embodiment. Additionally, the magnitude of a read pass voltage may depend on either the source line voltage or the location of the selected memory cell.

Compensating source side resistance versus word line

The present approach is based on the use of an integrated capacitance bridge circuit to measure the capacitance of a device under test. A significant feature of this approach is that the operating point is not the null point of the bridge circuit. Instead, the operating point of the bridge circuit is tuned to be away from the null point. By moving away from the null point, the output signal from the bridge circuit is increased. Preferably, this output signal is substantially larger than the input noise floor of an amplifier connected to the bridge circuit output, while being substantially less than G&#x3bd;, where G is the gain provided by the bridge circuit transistor and &#x3bd;is the AC signal applied to the device under test. Experiments on graphene devices and on carbon nanotube FETs demonstrate about 10 aF resolution (graphene) and about 13 aF resolution (carbon nanotube FET) at room temperature.

Integrated capacitance bridge for high-resolution wide-temperature-range capacitance measurement

Growing community of inventors

San Francisco, CA, United States of America

Arash Hazeghi